Well I made one back in 2003, in simulation at least. It was part of an EU funded project called poetic, which in short was making an fpga that could reprogram

Well I made one back in 2003, in simulation at least. It was part of an EU funded project called poetic, which in short was making an fpga that could reprogram itself for evolvable hardware purposes. (Alas the fabrication went off track a bit). At the suggestion of the designer Yann I made a growing delay line. The cpu would poke one cell of our fpga asking for a delay line N units long. This would create a single unit, then that cell would poke an adjacent cell and ask for a delay N-1 units long. Etc. The units could be anywhere on the chip and formed connections to one another with a hardware implementation of dijkstra's algorithm, iirc. When it was all connected you could start using the delay line. Not an efficient way to make a delay line, but definitely recursion. (Cross post from the se thread as I just noticed that's 7 years old) Update: here's a video I made of the simulation running. It's all verilog or vhdl under the hood. https://users.cs.cf.ac.uk/CooperCH/ontoroute.avi https://users.cs.cf.ac.uk/CooperCH/ontoroute.avi