You might find the QtRVSim simulator interesting: - WASM version: https://comparch.edu.cvut.cz/qtrvsim/app/ https://comparch.edu.cvut.cz/qtrvsim/app/ - source

You might find the QtRVSim simulator interesting: - WASM version: https://comparch.edu.cvut.cz/qtrvsim/app/ https://comparch.edu.cvut.cz/qtrvsim/app/ - source & native releases: https://github.com/cvut/qtrvsim https://github.com/cvut/qtrvsim It visualizes the inner workings of a basic RISC-V CPU, you can choose a basic single-cycle CPU, or a full 5-stage pipelined CPU with a hazard unit. I also recently wrote a 5-stage RISC-V CPU in SystemVerilog, the implementation should be reasonably well-commented: https://github.com/MatejKafka/risc-v_pipelined_cpu https://github.com/MatejKafka/risc-v_pipelined_cpu