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The old RISC vs CISC is completely dead now. Intel have now shown they can match ARM's equivalent powered CPUs in terms of energy efficiency, and that was the l

by berkut 15y ago

The old RISC vs CISC is completely dead now. Intel have now shown they can match ARM's equivalent powered CPUs in terms of energy efficiency, and that was the last argument the RISC proponents had in the argument. Intel's chips are internally RISC, with the only overhead of decoding and fusing the ops and the transistors to do this. And despite this overhead, they're still miles ahead. The only argument left then is the actual instruction sets at asm level, and here, CISC has an advantage, because they can do so much more in one instruction (take memory addressing modes for example), so they're more compact from an executable point-of-view and instruction cache point-of-view.

jules 15y ago
CISC isn't necessarily more compact. Since there are more instructions, each instruction takes up more space. For example in ARM's thumb encoding, each instruction takes up 16 bits. A typical x86 instruction takes much more space. I wonder how much of an x86 chip is dedicated to handling legacy instructions or largely unnecessary instructions. How much saving could be achieved by a radically simpler instruction set (for example no neg/call/ret/push/pop/bcd instructions). If you look at the http://en.wikipedia.org/wiki/X86_instruction_listings http://en.wikipedia.org/wiki/X86_instruction_listings then most of the instructions seem unnecessary. Does anybody have some information about this?
- anamax 15y ago
  > I wonder how much of an x86 chip is dedicated to handling legacy instructions or largely unnecessary instructions. How much saving could be achieved by a radically simpler instruction set (for example no neg/call/ret/push/pop/bcd instructions). It's been a long time since I was in a closely related biz, but back then, the answer was "not much if you want to go fast". Instruction decode isn't a huge deal. Micro-op sequencing isn't a big deal if you're going out of order (and many risc instructions tend to get broken into micro-ops). The number of architectural registers used to be a big thing, but X86_64 is good enough. (I don't know if anyone got around to renaming memory.)
- berkut 15y ago
  Okay, I probably should have been more specific - they might take up more memory, but you generally need less of them to do the same thing in RISC, so that usually more than compensates. Instruction decode isn't really difficult - 4-way decode could arguably be called difficult, but there's not much of that.
wolf550e 15y ago
Intel is beating ARM because Intel are a process ahead. If an Intel fab made ARM chips on the same process they use for i7s, that ARM chip would beat the pants off the Intel chip made on the same process. Intel does waste lots of chip real estate on caching big instructions (http://www.anandtech.com/show/3922/intels-sandy-bridge-architecture-exposed/2 http://www.anandtech.com/show/3922/intels-sandy-bridge-archi...) and on wide decoders that fault and go to microcode when they encounter some instructions. Think of how inefficient the SSE and AVX encodings are, because the need to escape 8086 code. Or the extra byte needed to access the extra 64bit registers. New CPUs are seldom limited by decoder width on regular code but it does cost watts and it costs space that could have been used for cache or for making the chip cheaper. I'm not even sure ARM is the best ISA. It doesn't matter which alternative is the best: I just predict that the best won't win because Intel will use their superiority in manufacturing to artificially boost the success of their lackluster CPU design guys.
- berkut 15y ago
  What are you talking about? Intel's 65nm (Pentium M) can still beat similarly clocked (1.5 Ghz) ARMs at 28nm - that's not due to process, that's due to a much more powerful architecture designed for speed over power consumption (Pentium M, then Core, Core 2). The instructions that fault are the very rarely used ones like weird string processing ones. Those are not going to be used in the middle of number-crunching loops. Escaping float ops hasn't been needed since the 486 days, so I'm not sure what on earth you're talking about. Intel's branch predicting and memory / cache pre-fetching are the best in the business. To say their CPUs are "lackluster CPU design", is pretty ridiculous, despite Atom being pretty crap.
  - wolf550e 15y ago
    > Intel's 65nm (Pentium M) can still beat similarly clocked (1.5 Ghz) ARMs at 28nm You can only compare chips that have the same power consumption. A 1w chip against a 45w (or whatever) chip is not a comparison you can make. Specifically, Intel now demonstrates a Penwell SoC with a Saltwell (Atom) core made on Intel's 32nm LP process and it benchmarks well against Cortex-A9 chips made on TSMC's 40nm process. I said that I guess that if Intel manufactured an ARM chip on Intel's 32nm LP process with the same die area and power consumption as their x86 chip, the ARM chip would be preferable. Like Anand said, We'll see how this SoC stacks up against multi-core Cortex-A15 chips on TSMC's 28nm process. If Intel changes the priority and makes their Low Power process transform to the next node together with (instead of after) the high-performance process (currently one step ahead at 22nm), then they will be seriously ahead of whoever manufactures ARM chips (TSMC and others). > The instructions that fault are the very rarely used ones They complicate the decoders and take up space and I think take up latency (clocks) during decoding. This costs money even when these instructions are not used. > Escaping ... so I'm not sure what on earth you're talking about REX prefix: http://www.x86-64.org/documentation/assembly.html http://www.x86-64.org/documentation/assembly.html > To say their CPUs are "lackluster CPU design", is pretty ridiculous Their power efficient design is in-order and pretty crap. You should read what Linus Torvalds had to say about it. Yes, Conroe was awesome and Sandy Bridge is awesome, but that is not what we're talking about here.

by berkut 15y ago

jules 15y ago

CISC isn't necessarily more compact. Since there are more instructions, each instruction takes up more space. For example in ARM's thumb encoding, each instruction takes up 16 bits. A typical x86 instruction takes much more space. I wonder how much of an x86 chip is dedicated to handling legacy instructions or largely unnecessary instructions. How much saving could be achieved by a radically simpler instruction set (for example no neg/call/ret/push/pop/bcd instructions). If you look at the http://en.wikipedia.org/wiki/X86_instruction_listings http://en.wikipedia.org/wiki/X86_instruction_listings then most of the instructions seem unnecessary. Does anybody have some information about this?

anamax 15y ago
> I wonder how much of an x86 chip is dedicated to handling legacy instructions or largely unnecessary instructions. How much saving could be achieved by a radically simpler instruction set (for example no neg/call/ret/push/pop/bcd instructions). It's been a long time since I was in a closely related biz, but back then, the answer was "not much if you want to go fast". Instruction decode isn't a huge deal. Micro-op sequencing isn't a big deal if you're going out of order (and many risc instructions tend to get broken into micro-ops). The number of architectural registers used to be a big thing, but X86_64 is good enough. (I don't know if anyone got around to renaming memory.)
berkut 15y ago
Okay, I probably should have been more specific - they might take up more memory, but you generally need less of them to do the same thing in RISC, so that usually more than compensates. Instruction decode isn't really difficult - 4-way decode could arguably be called difficult, but there's not much of that.

wolf550e 15y ago

Intel is beating ARM because Intel are a process ahead. If an Intel fab made ARM chips on the same process they use for i7s, that ARM chip would beat the pants off the Intel chip made on the same process. Intel does waste lots of chip real estate on caching big instructions (http://www.anandtech.com/show/3922/intels-sandy-bridge-architecture-exposed/2 http://www.anandtech.com/show/3922/intels-sandy-bridge-archi...) and on wide decoders that fault and go to microcode when they encounter some instructions. Think of how inefficient the SSE and AVX encodings are, because the need to escape 8086 code. Or the extra byte needed to access the extra 64bit registers. New CPUs are seldom limited by decoder width on regular code but it does cost watts and it costs space that could have been used for cache or for making the chip cheaper. I'm not even sure ARM is the best ISA. It doesn't matter which alternative is the best: I just predict that the best won't win because Intel will use their superiority in manufacturing to artificially boost the success of their lackluster CPU design guys.

berkut 15y ago
What are you talking about? Intel's 65nm (Pentium M) can still beat similarly clocked (1.5 Ghz) ARMs at 28nm - that's not due to process, that's due to a much more powerful architecture designed for speed over power consumption (Pentium M, then Core, Core 2). The instructions that fault are the very rarely used ones like weird string processing ones. Those are not going to be used in the middle of number-crunching loops. Escaping float ops hasn't been needed since the 486 days, so I'm not sure what on earth you're talking about. Intel's branch predicting and memory / cache pre-fetching are the best in the business. To say their CPUs are "lackluster CPU design", is pretty ridiculous, despite Atom being pretty crap.
- wolf550e 15y ago
  > Intel's 65nm (Pentium M) can still beat similarly clocked (1.5 Ghz) ARMs at 28nm You can only compare chips that have the same power consumption. A 1w chip against a 45w (or whatever) chip is not a comparison you can make. Specifically, Intel now demonstrates a Penwell SoC with a Saltwell (Atom) core made on Intel's 32nm LP process and it benchmarks well against Cortex-A9 chips made on TSMC's 40nm process. I said that I guess that if Intel manufactured an ARM chip on Intel's 32nm LP process with the same die area and power consumption as their x86 chip, the ARM chip would be preferable. Like Anand said, We'll see how this SoC stacks up against multi-core Cortex-A15 chips on TSMC's 28nm process. If Intel changes the priority and makes their Low Power process transform to the next node together with (instead of after) the high-performance process (currently one step ahead at 22nm), then they will be seriously ahead of whoever manufactures ARM chips (TSMC and others). > The instructions that fault are the very rarely used ones They complicate the decoders and take up space and I think take up latency (clocks) during decoding. This costs money even when these instructions are not used. > Escaping ... so I'm not sure what on earth you're talking about REX prefix: http://www.x86-64.org/documentation/assembly.html http://www.x86-64.org/documentation/assembly.html > To say their CPUs are "lackluster CPU design", is pretty ridiculous Their power efficient design is in-order and pretty crap. You should read what Linus Torvalds had to say about it. Yes, Conroe was awesome and Sandy Bridge is awesome, but that is not what we're talking about here.