4 ms·
Sometimes such 'redundant' instructions happen because of incomplete instruction decoding. For instance the ED-prefixed instruction block on the Z80 has: - 8x
by flohofwoe 4y ago
Sometimes such 'redundant' instructions happen because of incomplete instruction decoding. For instance the ED-prefixed instruction block on the Z80 has:
- 8x NEG
- 8x RETI/RETN (named differently but same behaviour)
- 4x IM0, 2x IM1 and 2x IM2
- and a whopping 178 opcodes in the ED block decode to a NOP (no operation)