3 ms·
Most implementations announced recently (e.g. in RISC-V Summit last December) have B. Even the newer revisions of cores that have been available for a while (l
by snvzz 4y ago
Most implementations announced recently (e.g. in RISC-V Summit last December) have B.
Even the newer revisions of cores that have been available for a while (like SiFive U74) have been updated with B support.
As such, I believe it to be a non-issue. Hardware simply takes time.
>which are difficult to prove their value as a result,
As with any RISC-V extensions, each instruction had to meet many criteria to be allowed in there.
Rationale accompany the instructions in the documentation.
- nullc 4y ago> Most implementations announced recently (e.g. in RISC-V Summit last December) have B. That's fantastic. > Rationale accompany the instructions in the documentation. I've read it-- I didn't personally need it to be convinced, but I'm surprised it convinced vendors. Glad to hear that it has.