It could look like the DRAM is the problem if the data bus was the actual problem, as the DMA would request data via the bus. This is just speculation here obvi

It could look like the DRAM is the problem if the data bus was the actual problem, as the DMA would request data via the bus. This is just speculation here obviously. But if you have lots of hardware on a tri-state bus most of which is not of "data centre" quality then it wouldn't be unusual for bus arbitration to go out the window in a fluctuating power condition. So from the DMA through to write operation you have data corruption issues, and you'd think it was probably the DRAM but in fact if the bus arbitration is corrupted then you still get corrupted data. I suspect sure that the vast majority of PCs don't have error detection (let alone ECC) on their data buses (even something as simple as a parity bit), but I could be wrong.