4 ms·
> when power drops, and the voltage levels on the power rails start drooping, DRAM tends to go insane and starts returning garbage long before the DMA engine an
by magnat 4y ago
> when power drops, and the voltage levels on the power
rails start drooping, DRAM tends to go insane and starts returning
garbage long before the DMA engine and the hard drive stops
functioning
That doesn't sound right. DRAM can keep its content for a few seconds without power - it's what make Cold boot attacks [1] possible. Also, DRAM has its own buck voltage regulators, usually with hefty inductors, capable of delivering power long after +5V and +12V started to drop.
[1] https://en.wikipedia.org/wiki/Cold_boot_attack https://en.wikipedia.org/wiki/Cold_boot_attack
- tankenmate 4y agoIt could look like the DRAM is the problem if the data bus was the actual problem, as the DMA would request data via the bus. This is just speculation here obviously. But if you have lots of hardware on a tri-state bus most of which is not of "data centre" quality then it wouldn't be unusual for bus arbitration to go out the window in a fluctuating power condition. So from the DMA through to write operation you have data corruption issues, and you'd think it was probably the DRAM but in fact if the bus arbitration is corrupted then you still get corrupted data. I suspect sure that the vast majority of PCs don't have error detection (let alone ECC) on their data buses (even something as simple as a parity bit), but I could be wrong.
- nicolaslem 4y agoHaving memory return a few bits flipped can have disastrous consequences on a running system. On the other hand having memory with only a few bits flipped is still a gold mine for a cold boot attack.