Shift registers are an interesting option. They are obviously feasible, especially if using ones with a built in pull-down. They do avoid having a diode per ke

Shift registers are an interesting option. They are obviously feasible, especially if using ones with a built in pull-down. They do avoid having a diode per key, in exchange for needing a chip for N keys, where n is the number of of parallel inputs in your parallel to serial shift register. They can also save IO lines. Obviously with if using chainable shift registers, you can have an unlimited number of keys with just 3 IO lines. More realistic of course, would be to use several IO lines in parallel. For a 64 key matrix, one could say use 8, 8-bit shift registers, each connected to one input line, plus one output latch line and one output clock line (for a total of 10), vs the 16 lines needed traditional matrix. 8 input lines is nice, because if you pick the I/O lines right, retrieving the values is just a single port read. Making the procedure: latch, (toggle clock twice, read port, write to next location in memory buffer) x8. There are of course downsides, like shift registers needing more board space than tiny surface mount diodes, but this is not necessarily a deal-killer.