3 ms·
Careful, you're coming dangerously close to reinventing SystemVerilog's formal verification support :) SV formal is tough at first but wonderful once you really
by sweetjuly 4y ago
Careful, you're coming dangerously close to reinventing SystemVerilog's formal verification support :) SV formal is tough at first but wonderful once you really get it because it lets you lay out your constraints and preconditions and then the solver verifies that your circuit fulfills those requirements.