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> But RISC did change everything, didn't it? Iirc it's not such a meaningful distinction anymore. "CISC" x86 uses micro-operations internally. "RISC" ARM has s

> But RISC did change everything, didn't it? Iirc it's not such a meaningful distinction anymore. "CISC" x86 uses micro-operations internally. "RISC" ARM has several different instruction encodings (ARM, Thumb, Thumb-2, A64). Increasing numbers of people are working in high level languages anyway.

msla 4y ago
> "CISC" x86 uses micro-operations internally. Like generations of CISC before it. That doesn't make it any less CISC. https://userpages.umbc.edu/~vijay/mashey.on.risc.html https://userpages.umbc.edu/~vijay/mashey.on.risc.html From that page, which collects a number of Usenet posts by John Mashey: > The RISC characteristics: > a) Are aimed at more performance from current compiler technology (i.e., enough registers). > OR > b) Are aimed at fast pipelining > - in a virtual-memory environment > - with the ability to still survive exceptions > - without inextricably increasing the number of gate delays (notice that I say gate delays, NOT just how many gates). The point b is where RISC chips really pulled away from CISC in terms of architectural design, especially chips like the MIPS, which Mashey worked on: The MIPS had a number of points where it exposed the tricks it used to pipeline more aggressively, even at the expense of making compilers somewhat harder to write and/or human assembly-language programmers think a bit harder. However, the lack of complicated addressing modes (post-increment, scale-and-offset, etc.) and the lack of register-memory opcodes with ALU operations, and total lack of memory-memory operations, is still a very common feature of RISC design.
bee_rider 4y ago
That seems like RISC changing everything. How much did it change things? CISC has been transformed from a true competitor to RISC to a sort of abstraction layer on top of it.
- astrange 4y ago
  That's not really true. x86 chips are not secretly RISC inside; the microcode often corresponds to individual instructions, it has complex things like 'lea' that are quite efficient, and you can't really abstract away things like variable length instructions.
astrange 4y ago
AArch64 only has one instruction encoding. I think it's a bit too complex to be RISC though. On the other hand, it's simpler than ARMv7 - not just because of getting rid of Thumb, it also doesn't have conditional execution.

msla 4y ago

> "CISC" x86 uses micro-operations internally. Like generations of CISC before it. That doesn't make it any less CISC. https://userpages.umbc.edu/~vijay/mashey.on.risc.html https://userpages.umbc.edu/~vijay/mashey.on.risc.html From that page, which collects a number of Usenet posts by John Mashey: > The RISC characteristics: > a) Are aimed at more performance from current compiler technology (i.e., enough registers). > OR > b) Are aimed at fast pipelining > - in a virtual-memory environment > - with the ability to still survive exceptions > - without inextricably increasing the number of gate delays (notice that I say gate delays, NOT just how many gates). The point b is where RISC chips really pulled away from CISC in terms of architectural design, especially chips like the MIPS, which Mashey worked on: The MIPS had a number of points where it exposed the tricks it used to pipeline more aggressively, even at the expense of making compilers somewhat harder to write and/or human assembly-language programmers think a bit harder. However, the lack of complicated addressing modes (post-increment, scale-and-offset, etc.) and the lack of register-memory opcodes with ALU operations, and total lack of memory-memory operations, is still a very common feature of RISC design.

bee_rider 4y ago

That seems like RISC changing everything. How much did it change things? CISC has been transformed from a true competitor to RISC to a sort of abstraction layer on top of it.

astrange 4y ago
That's not really true. x86 chips are not secretly RISC inside; the microcode often corresponds to individual instructions, it has complex things like 'lea' that are quite efficient, and you can't really abstract away things like variable length instructions.

astrange 4y ago

AArch64 only has one instruction encoding. I think it's a bit too complex to be RISC though. On the other hand, it's simpler than ARMv7 - not just because of getting rid of Thumb, it also doesn't have conditional execution.