4 ms·
Do we know what instruction-set profile it implements? Any?
by moloch-hai 4y ago
Do we know what instruction-set profile it implements? Any?
- snvzz 4y agoI understand it's RV64GCB + a few Z extensions. As RVA22 is not done (although almost there), we can't know whether it's compliant, but we will once it is. Expectation is yes. Otherwise, most stuff out there will be RVA20 compliant once that's ratified, as that reflects what was already common back in chips designed in 2020, what most have been calling RV64GC.
- moloch-hai 4y agoThank you. Guessing the Z extensions are AES operations? Supervisor ops?
- snvzz 4y agoThe cores are SiFive U74-MC, the version is, I believe, 21G1. These are documented. But that design is configurable. We know B extension (optional) is enabled. I have no idea about every other setting this core can be synthesized with.
- snvzz 4y agoUpdate: B extension is apparently not actually enabled. Alas.
- moloch-hai 4y agoAs usual. Sigh. Just Zpopcnt would go a long way.
- snvzz 4y agoIt might have popcnt. It might have Za and Zb. It just doesn't claim to have B (the whole package).
- moloch-hai 4y agoLooks like Zbb is where the "CPOP" and related instructions (popcount, count leading/trailing zeroes) live. Zba ("and-not" etc.) and Zbs (single-bit) are more obscure and less important. Zbc (carry-less multiply) is interesting.
- Taniwha 4y agomore like generic tweaks rather than large swathes of stuff
- zu2_ 4y ago$ cat /proc/cpuinfo processor : 0 hart : 2 isa : rv64imafdc mmu : sv39 uarch : sifive,u74-mc
- moloch-hai 4y agoAny clue on Zbb? Zk* and Zbk*? Can you do regular Linux without S?