Chisel is compiled to Verilog so it has excellent interoperability. You can use Chisel in an existing Verilog project or use existing Verilog modules in a Chise

Chisel is compiled to Verilog so it has excellent interoperability. You can use Chisel in an existing Verilog project or use existing Verilog modules in a Chisel project. Therefore it is already supported by practically all vendors and simulators. I've used Chisel to interface with proprietary Lattice DSPs and RAM modules, and I'm sure you could do the same with other vendors as well. All you have to do is define the IOs and parameters of the module. In Chisel this is called a "Blackbox". Example: https://github.com/fayalalebrun/6502-exp/blob/master/src/main/scala/blackbox/LatticeFIFO.scala https://github.com/fayalalebrun/6502-exp/blob/master/src/mai...