17 ms·
8086 Processor's microcode pipeline from die analysis
- IYasha 4y ago[flagged]
- kens 4y agoAuthor here to answer all your 8086 questions :-)
- fsckboy 4y agosort of a side question, but with all these projects excavating old dies (which are intensely interesting, don't get me wrong), I'm curious if any of the engineers who worked on this stuff originally (such a short time ago) ever pop up to explain how and or why it was done how it was done this way or that?
- kens 4y agoI've talked to some of the engineers to get background on the design of the 8086 chip. They also wrote some papers at the time explaining why things were done particular ways. The 8086 patents are also very detailed; many older patents actually provide a lot of useful information. Patent: https://patents.google.com/patent/US4449184A https://patents.google.com/patent/US4449184A
- db48x 4y agoEverything stalls while waiting for memory.
- jason_s 4y agoBill Mensch and Albert Charpentier have had discussions posted on YouTube about the 6502 and VIC-II chips, respectively.
- rwmj 4y agoWhen you look at the die shots, do you get any idea of how the masks were drawn in those days? I assume computers of the day would not have been powerful enough for a CAD tool to design a silicon or metal layer of that complexity. Were they designed in smaller parts and then stitched together into a final design? -- perhaps evident by different parts having different design styles, or not quite using all the space between functional units. Were all parts done on a computer, or some pieces hand-drawn?
- collectordrx 4y agoI can perhaps give some insight into this. One step in the mask making process was hand cutting the design into a masking film called Rubylith. Rubylith is made of a backing sheet coated in a UV resistant red film. The design was hand cut into this film on a large scale then used as a “master” to expose smaller copies.
- kens 4y agoThere's a detailed article "Recollections of Early Chip Development at Intel". For the first 10 years, Intel drew schematics and layout by hand. In 1974 they started digitizing on a Calma GDS I system. For the 8086, they spent two weeks manually matching the schematics against the drawn plots looking for errors and found 20 errors. They cut out the drawings on sheets of Rubylith to create the masks. The earliest chips used a "Coordinatograph", a tool where you'd manually enter the coordinates from the drawing and it would move the cutter appropriately. Then they moved to a Xynetics plotter with a knife. The Rubylith sheets would be sent to the mask vendor, who would photographically reduce it down to mask size. Intel had simulation tools, but they could only simulate 5-20 transistors at a time. So they could only simulate small, critical chunks like parts of the ALU. https://www.intel.com/content/dam/www/public/us/en/documents/research/2001-vol05-iss-1-intel-technology-journal.pdf https://www.intel.com/content/dam/www/public/us/en/documents...
- rwmj 4y agoIn case you haven't seen it (although I'm sure you have), Now The Chips Are Down had a rare look inside an Intel fab in the 1970s: https://en.wikipedia.org/wiki/Now_the_Chips_Are_Down https://en.wikipedia.org/wiki/Now_the_Chips_Are_Down There are copies of the film on the internet.
- toinewx 4y agobit off-topic but what you do is inspiring, you are the kind of person that makes me think "damn its crazy what human can do". We are lucky to have you
- PaulHoule 4y agoI like how the microcode is a bit like VLIW in that each instruction has a move AND and action that are done in two parallel systems simultaneously.
- kens 4y agoYes, the 8086 microcode does get some parallelism, but it's a pretty short Very Long Instruction Word :-) An 8086 micro-instruction is just 21 bits long, while VLIW words are much longer. I'm studying the IBM System/360 Model 50 and its micro-instructions are 90 bits long. A Model 50 micro-instruction is so complex with 28 different fields that it isn't represented by a line of code, but an 11-line block of code.
- PaulHoule 4y agoThe 8086 is just starting to pipeline so it is starting small. Recently I did some reading about the Transport Triggered Architecture and for the first time thought "I could make a special purpose microprocessor" and might actually try it with an FPGA. That got me thinking a lot about processor architecture, particularly the ability for one (real or micro) instruction to simultaneously control multiple subsystems. What I see as problematic though is that the TTA stalls when it is waiting for memory, I think a high performance system based on the TTA would need some kind of programmable memory access engine that would try to schedule fetches ahead of time programmatically... But I think then it is getting pretty hard.
- LargoLasskhyfv 4y agoHave you seen https://github.com/MicroCoreLabs/Projects https://github.com/MicroCoreLabs/Projects from http://www.microcorelabs.com/about.html http://www.microcorelabs.com/about.html ? Some of them implement 'Microsequencing' ( https://en.wikipedia.org/wiki/Microsequencer https://en.wikipedia.org/wiki/Microsequencer ) which could maybe be useful? Conceptually, I mean.
- psychphysic 4y agoCan't access :/ Ukraine's blocked?
- deleted 4y ago[deleted]
- kens 4y agoThat's strange. Can you send me your IP address and I'll take a look?
- fnordpiglet 4y ago[flagged]
- kramerger 4y agoSorry, but you don't happen to be a famous bending robot by any chance? On a more serious note, the pipeline layout could be a side effect of how Shima worked with logic and transistor layout simultaneously (he was not involved in 8086, but a lot of design came from his 8080) https://en.m.wikipedia.org/wiki/Masatoshi_Shima https://en.m.wikipedia.org/wiki/Masatoshi_Shima
- deleted 4y ago[deleted]
- userbinator 4y agoIt's interesting to read these articles about the implementation of an actual CPU, compared to the very idealised perspective that a lot of CS (and even some hardware-oriented) textbooks have. There's a lot of complexity that those who are used to the latter would otherwise not have seen. Also worth noting is that, like the Z80 and 8080/8085, but unlike the 6502, the designers of the 8086 opted for instructions that took more cycles and compensated for that with increased clock frequency, instead of the 6502 that has shorter instructions and a lower clock frequency. and the hardware fills in the particular ALU operation from bits 5-3 of the machine instruction. This is clearly seen when the instructions are represented in octal: 0u4 alu AL, imm8 0u5 alu AX, imm16 The ALU operations are respectively: ADD, OR, ADC, SBB, AND, SUB, XOR, CMP. According to the datasheets, the 80186 can execute the same instruction in 3 cycles, and the 80286 can do it in 2.
- anyfoo 4y ago> instead of the 6502 that has shorter instructions and a lower clock frequency. The 6502 is a simpler CPU, 8 bit wide with less registers and less instructions. It uses a PLA instead of microcode, presumably because it still could get away with that.
- MatteoFrigo 4y agoIf you are interested in this topic, the book "The Anatomy of a High-Performance Microprocessor: A Systems Perspective" by Bruce Shriver and Bennett Smith describes the architecture of the AMD K6 processor (late '90s) in detail, including the structure of the pipeline and microcode.