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Verilog does make it fantastically easy to create bugs! It feels like very early C versions that are way too lenient. The biggest bang-for-the-buck you can get
by bajsejohannes 4y ago
Verilog does make it fantastically easy to create bugs! It feels like very early C versions that are way too lenient. The biggest bang-for-the-buck you can get here is adding "`default_nettype none" at the top of every file, which makes undeclared identifiers an error. I believe this is SystemVerilog, though, and I agree that's what you should learn.
- _0ffh 4y agoThe default_nettype directive is at least in the Verilog 2001 standard. Ed. Seems it's in Verilog-1995, too: http://www.csit-sun.pub.ro/~duca/cn/verilog_ref_guide/vlog_ref_top.html http://www.csit-sun.pub.ro/~duca/cn/verilog_ref_guide/vlog_r...