RISC-V would be seen as an "average" modern ISAs. Like everything, it comes with trade-offs, and here some ISA design choices come straight from the experience

RISC-V would be seen as an "average" modern ISAs. Like everything, it comes with trade-offs, and here some ISA design choices come straight from the experience accumulated on advanced CPU design. For instance, if I did understand well, the handling of arithmetics flags in RISC-V is what it is because of it makes out-of-order CPU design way easier.