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specter and friends showed us, again, that "security" is a fantasy. I would not expect anything different from RISC-V CPU designs. BTW, are specter and friend
by sylware 4y ago
specter and friends showed us, again, that "security" is a fantasy.
I would not expect anything different from RISC-V CPU designs.
BTW, are specter and friends fixed in Zen4?
- willnonya 4y agoThe problem is that this only applies to the design and not the implementation. There is no perfect design and certainly no perfect implementations.
- sylware 4y agoRISC-V would be seen as an "average" modern ISAs. Like everything, it comes with trade-offs, and here some ISA design choices come straight from the experience accumulated on advanced CPU design. For instance, if I did understand well, the handling of arithmetics flags in RISC-V is what it is because of it makes out-of-order CPU design way easier.
- snvzz 4y ago>specter and friends showed us, again, that "security" is a fantasy. >I would not expect anything different from RISC-V CPU designs. Look into `fence.t` [0]. 0. https://youtu.be/C3nOjXhyPfk?list=PLtoQeavghzr3atxNQig-sLGbwoKBSVxGV&t=1171 https://youtu.be/C3nOjXhyPfk?list=PLtoQeavghzr3atxNQig-sLGbw...