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Why not a single FPGA with 100Gbps ethernet or pcie with NVM attached? Around $5K for the hardware and $5K for the traffic per month. The software would be a bi

Why not a single FPGA with 100Gbps ethernet or pcie with NVM attached? Around $5K for the hardware and $5K for the traffic per month. The software would be a bit trickier to write, but you now get 100x performance for the same price

tluyben2 4y ago
That would be quite a nice project for fun.
- morphle 4y ago
  I have seen a number of papers of people doing such a fun project as their PhD thesis. I'll try to find some more [1] examples with links on Google Scholar. Try searching for p4 programmable dataplane content address". [1] Flexible Content-based Publish/Subscribe over Programmable Data Planes https://pure.rug.nl/ws/files/206093441/Flexible_Content_based_Publish_Subscribe_over_Programmable_Data_Planes.pdf https://pure.rug.nl/ws/files/206093441/Flexible_Content_base...
mpoteat 4y ago
Let's spend multi-million dollars a year on a team of highly specialized FPGA engineers writing assembly and HDL so that we can save 5k a month. Feature velocity will be 100x slower as well, but at least our application is efficient. I think that this may make sense for some applications, but I also think that if you can utilize software abstractions to improve developer efficiency, it reduces risk in the long run.
- morphle 4y ago
  Those millions of dollars have already been spent. For example the P4 [1] language (a HDL language) and the Tofino 3 chip. It started out as FPGA (NetFPGA) to do programmable packet routing at linespeed. You now have the P4 language to define your packet routers with and generate your code. Ten years later we have 25 Tbps software defined packet routers. [1] https://en.wikipedia.org/wiki/P4_(programming_language) https://en.wikipedia.org/wiki/P4_(programming_language) [2] https://www.intel.com/content/www/us/en/products/network-io/programmable-ethernet-switch/tofino-3-brief.html https://www.intel.com/content/www/us/en/products/network-io/...
- nimish 4y ago
  >Let's spend multi-million dollars a year on a team of highly specialized FPGA engineers I agree with you specialists are expensive but even a team of software engineers runs into the multi million dollar territory. Why not spend the same amount AND cut down resource use? Hyperscalers have shifted to custom hardware already.
tylerhou 4y ago
A bit trickier is a huge understatement.
- morphle 4y ago
  That depends. If you would use our asynchronous runtime reconfigurable array called Morphle Logic [1] instead of FPGA (Field Programmable Gate Array), you could program this hardware Twitter in a 1000 hours and have it run at 50 Tbps. You would not need to know much about hardware but you would get a thousandfold speedup of your software. [1] https://github.com/fiberhood/MorphleLogic/blob/main/README_MORPHLE_LOGIC.md https://github.com/fiberhood/MorphleLogic/blob/main/README_M...

tluyben2 4y ago

That would be quite a nice project for fun.

morphle 4y ago
I have seen a number of papers of people doing such a fun project as their PhD thesis. I'll try to find some more [1] examples with links on Google Scholar. Try searching for p4 programmable dataplane content address". [1] Flexible Content-based Publish/Subscribe over Programmable Data Planes https://pure.rug.nl/ws/files/206093441/Flexible_Content_based_Publish_Subscribe_over_Programmable_Data_Planes.pdf https://pure.rug.nl/ws/files/206093441/Flexible_Content_base...

mpoteat 4y ago

Let's spend multi-million dollars a year on a team of highly specialized FPGA engineers writing assembly and HDL so that we can save 5k a month. Feature velocity will be 100x slower as well, but at least our application is efficient. I think that this may make sense for some applications, but I also think that if you can utilize software abstractions to improve developer efficiency, it reduces risk in the long run.

morphle 4y ago
Those millions of dollars have already been spent. For example the P4 [1] language (a HDL language) and the Tofino 3 chip. It started out as FPGA (NetFPGA) to do programmable packet routing at linespeed. You now have the P4 language to define your packet routers with and generate your code. Ten years later we have 25 Tbps software defined packet routers. [1] https://en.wikipedia.org/wiki/P4_(programming_language) https://en.wikipedia.org/wiki/P4_(programming_language) [2] https://www.intel.com/content/www/us/en/products/network-io/programmable-ethernet-switch/tofino-3-brief.html https://www.intel.com/content/www/us/en/products/network-io/...
nimish 4y ago
>Let's spend multi-million dollars a year on a team of highly specialized FPGA engineers I agree with you specialists are expensive but even a team of software engineers runs into the multi million dollar territory. Why not spend the same amount AND cut down resource use? Hyperscalers have shifted to custom hardware already.

tylerhou 4y ago

A bit trickier is a huge understatement.

morphle 4y ago
That depends. If you would use our asynchronous runtime reconfigurable array called Morphle Logic [1] instead of FPGA (Field Programmable Gate Array), you could program this hardware Twitter in a 1000 hours and have it run at 50 Tbps. You would not need to know much about hardware but you would get a thousandfold speedup of your software. [1] https://github.com/fiberhood/MorphleLogic/blob/main/README_MORPHLE_LOGIC.md https://github.com/fiberhood/MorphleLogic/blob/main/README_M...