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We have designed several versions of Morphle Logic asynchronous runtime reconfigurable arrays. They can do the same as FPGA's but are not exactly the same gate

We have designed several versions of Morphle Logic asynchronous runtime reconfigurable arrays. They can do the same as FPGA's but are not exactly the same gate arrays, as explaind in this readme: https://github.com/fiberhood/MorphleLogic/blob/main/README_MORPHLE_LOGIC.md https://github.com/fiberhood/MorphleLogic/blob/main/README_M... You can add Morphle Logic to any processor including RISC-V and program/reconfigure the gate array by just writing SRAM. So you can reprogram small parts in nanoseconds if you want, even while the circuit is running! We've added a small RISC-V processor to make it easy to reprogram the Morphle Logic. There is a small caveat: you can not buy our chips yet... I need $100K and 3 months to tape out new chips first. An equivalent Morphle Logic of a small FPGA like the ICE40 would cost half a dollar, the equivalent of an Virtex Ultrascale would cost around $600. Some parts of these reconfigurable arrays could run at 12 Ghz. Email us at morphle [at] ziggo { dot} nl

gradschool 4y ago
I'm a big fan of asynchronous design, though more as a spectator than a participant in recent years, and I'm really glad to see a bold new idea like yours because I was beginning to wonder whether the whole field had been stagnating. If there's anything else you want to share publicly about your work I'm all ears. I'm particularly curious about how you've coped with arbitration or contention in on-chip packet switched networks, or whether the issue ever came up. BTW, cloudflare says your web site is not responding as of 20:39 UTC, January 9.
- fiberhood 4y ago
  Our main project is an asynchronous wafer scale integration, a 1000 core asynchronous processors with 300 Megabyte of asynchronous SRAM (300 Kilobyte per core) and a huge Morphle Logic, our ‘asynchronous’ gate array. A $600 supercomputer running Squeak Smalltalk and a GUI. The second is a $5 10 core processor with 6 Megabyte memory for IoT, gigabit ethernet and Morphle Logic to compress video streams Squeak Smalltalk over ethernet. Much faster than a Raspberry PI 4 with a 4K camera, but not $100 but just $5 total cost. > though more as a spectator than a participant in recent years, That is a pity, I was hoping you would be a grad student or similar that could do a Masters or PhD thesis writing our software for the asynchronous manycore processor and the ‘asynchronous’ gate array. Maybe you can help me locate another student who would do his masters with us? Any volunteer would be helpful, it's just that we don't pay any salaries. But we do hand out samples...... I had a lecture on a larger version of this, a million core wafer scale integration running Smalltalk: https://vimeo.com/731037615 https://vimeo.com/731037615

gradschool 4y ago

I'm a big fan of asynchronous design, though more as a spectator than a participant in recent years, and I'm really glad to see a bold new idea like yours because I was beginning to wonder whether the whole field had been stagnating. If there's anything else you want to share publicly about your work I'm all ears. I'm particularly curious about how you've coped with arbitration or contention in on-chip packet switched networks, or whether the issue ever came up. BTW, cloudflare says your web site is not responding as of 20:39 UTC, January 9.

fiberhood 4y ago
Our main project is an asynchronous wafer scale integration, a 1000 core asynchronous processors with 300 Megabyte of asynchronous SRAM (300 Kilobyte per core) and a huge Morphle Logic, our ‘asynchronous’ gate array. A $600 supercomputer running Squeak Smalltalk and a GUI. The second is a $5 10 core processor with 6 Megabyte memory for IoT, gigabit ethernet and Morphle Logic to compress video streams Squeak Smalltalk over ethernet. Much faster than a Raspberry PI 4 with a 4K camera, but not $100 but just $5 total cost. > though more as a spectator than a participant in recent years, That is a pity, I was hoping you would be a grad student or similar that could do a Masters or PhD thesis writing our software for the asynchronous manycore processor and the ‘asynchronous’ gate array. Maybe you can help me locate another student who would do his masters with us? Any volunteer would be helpful, it's just that we don't pay any salaries. But we do hand out samples...... I had a lecture on a larger version of this, a million core wafer scale integration running Smalltalk: https://vimeo.com/731037615 https://vimeo.com/731037615