Same. Alas, sensing the contents of a DRAM cell in the time allotted is already a tough ask. Having to discriminate between multiple voltage levels would surel

Same. Alas, sensing the contents of a DRAM cell in the time allotted is already a tough ask. Having to discriminate between multiple voltage levels would surely make have a nasty latency impact. OTOH, I believe DRAM senses entire rows at a time -- so after that latency hit, bandwidth might be unchanged. Any idea if it is even possible with existing capacitive DRAM cells?