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> Sure, wouldn't want to starve the GPU when the CPU is busy. Ok, then surely you won't take issue with me describing my x86 desktop as having 1.2TB/s of memor

> Sure, wouldn't want to starve the GPU when the CPU is busy. Ok, then surely you won't take issue with me describing my x86 desktop as having 1.2TB/s of memory bandwidth? It just happens to be in a NUMA configuration and after all, wouldn't want to starve the GPU when the CPU is busy... > Don't see a particular difference. You don't see a difference between 1 memory controller and 2 memory controllers? Compare Zen1 TR/epyc vs. zen2 TR/epyc. Hint: m1 ultra is like Zen1, and probably ain't the future Oh yeah and Intel did this, too, with the 56 core xeons a couple years ago. And, like AMD, also quickly moved away from it.

sliken 4y ago
> Ok, then surely you won't take issue with me describing my x86 desktop as having 1.2TB/s of memory bandwidth? Unless it's a rather odd config that's counting the GPU memory bandwidth which is decidedly not NUMA since the GPU mem isn't cache coherent with the main memory. > You don't see a difference between 1 memory controller and 2 memory controllers? From what I can tell the multiple memory controllers per chip AMDs performed well on most codes, but certain codes, OSs, and benchmarks didn't handle the different latencies within the socket well. As a result AMD moved to one memory controller per socket in the next generation. The M1 ultra moved to two chips and 2 memory controllers, but as a result manages to hit 800GB/sec peak which is a pretty big win compared to any normal socket, even the 96 core AMD Genoa or Intel SPR are sitting in the half to 1/3rd range, despite coming our a year or so later.