3 ms·
Vector length agnostic programming has its own share of problems. I'm not familiar with the RISC-V V extension, but I assume it's similar to ARM's SVE. There's
by chris6f 4y ago
Vector length agnostic programming has its own share of problems. I'm not familiar with the RISC-V V extension, but I assume it's similar to ARM's SVE. There's a good critical look at SVE and VLA here: https://gist.github.com/zingaburga/805669eb891c820bd220418ee3f0d6bd#fixed-width-vector-workloads-on-variable-width-vectors https://gist.github.com/zingaburga/805669eb891c820bd220418ee...
- snvzz 4y agoV extension and SVE2 are very different. Here is a quite recent introduction to RISC-V Vector[0]. 0. https://erikexplores.substack.com/p/grokking-risc-v-vector-processing https://erikexplores.substack.com/p/grokking-risc-v-vector-p...
- janwas 4y agoI'm curious why you say they are very different? From where I sit, RVV also supports mask-like predication, and adds two concepts: LMUL (in-HW unrolling of each instruction) plus the ability to limit operations to a given number of elements. The former is nifty, though intended for single-issue machines, and the latter seems redundant because masks can also do that.