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How does cycle counting interact with CPU frequency scaling? Do you just assume that the CPU is at a fixed frequency for performance comparisons & analysis? (I

How does cycle counting interact with CPU frequency scaling? Do you just assume that the CPU is at a fixed frequency for performance comparisons & analysis? (I suppose this is accurate for short lived benchmarks.) I imagine you'd see some weird effects if the CPU changed its frequency during a benchmark, or if the process moved between cores since (as I understand it) the RAM would get faster relative to the CPU when the CPU is clocked lower. So some operations would take fewer cycles when the CPU is running slower. Or am I misunderstanding what this is measuring?

deleted 4y ago
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jpk 4y ago
The cycle counters are a just monotonically incrementing values, so polling them just lets you calculate the average effective frequency over the poll interval. You're right that stuff like i/o might happen in different numbers of cycles depending on actual frequency, but those operations generally take the same amount of wall time either way, so it comes out in the wash.
lucian-g 4y ago
It depends on the implementation: https://cpucycles.cr.yp.to/counters.html https://cpucycles.cr.yp.to/counters.html - default-perfevent: the kernel will keep track of counter values on core moves - amd64-pmc: Accesses a cycle counter through RDPMC: best to pin the benchmark binary to a specific core to avoid measurement issues when the task moves between cores: "taskset -c 1 <benchmark-binary>" - amd64-tsc, amd64-tscasm: RDTSC is off-core counter - not influenced by cross-core moves ("On current CPUs, this is an off-core clock rather than a cycle counter, but it is typically a very fast off-core clock, making it adequate for seeing cycle counts if overclocking and underclocking are disabled.")
bmh 4y ago
The short answer is: Yes, you must disable CPU frequency scaling in your BIOS if you're doing this kind of work (i.e. building cryptographic primitives that don't leak information via timing). See https://timing.attacks.cr.yp.to/overclocking.html https://timing.attacks.cr.yp.to/overclocking.html

deleted 4y ago

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jpk 4y ago

The cycle counters are a just monotonically incrementing values, so polling them just lets you calculate the average effective frequency over the poll interval. You're right that stuff like i/o might happen in different numbers of cycles depending on actual frequency, but those operations generally take the same amount of wall time either way, so it comes out in the wash.

lucian-g 4y ago

It depends on the implementation: https://cpucycles.cr.yp.to/counters.html https://cpucycles.cr.yp.to/counters.html - default-perfevent: the kernel will keep track of counter values on core moves - amd64-pmc: Accesses a cycle counter through RDPMC: best to pin the benchmark binary to a specific core to avoid measurement issues when the task moves between cores: "taskset -c 1 <benchmark-binary>" - amd64-tsc, amd64-tscasm: RDTSC is off-core counter - not influenced by cross-core moves ("On current CPUs, this is an off-core clock rather than a cycle counter, but it is typically a very fast off-core clock, making it adequate for seeing cycle counts if overclocking and underclocking are disabled.")

bmh 4y ago

The short answer is: Yes, you must disable CPU frequency scaling in your BIOS if you're doing this kind of work (i.e. building cryptographic primitives that don't leak information via timing). See https://timing.attacks.cr.yp.to/overclocking.html https://timing.attacks.cr.yp.to/overclocking.html