3 ms·

5950X hit its highest clocks on cores 1 and 4. Both are located on the first CCD. My 3950X clocked highest on cores 4 and 5. Both are also on the first CCD. Thi

by jagrsw 4y ago

5950X hit its highest clocks on cores 1 and 4. Both are located on the first CCD. My 3950X clocked highest on cores 4 and 5. Both are also on the first CCD. This is a curious pattern. Perhaps AMD is only binning one CCD to hit the maximum boost clocks on 16 core parts. I have 5950X and saw this pattern, the fastest cores are though 2nd and 6th (starting from 0). I don't remember exact values from testing (with stress-ng and openssl speed), but it was something similar to what authors observed in their testing. Those two cores were able to reach speeds of around 4.97, the next ones 4.95 or so, with the slowest pair stuck at around 4.7GHz.

Rarebox 4y ago
This would make sense right? You probably can't run all cores at max turbo frequency before hitting power and thermal limits. So dividing chiplets based on binning would result in good performance for 1-8 -threaded tasks while reducing chip lottery. (But it's possible there are other reasons for the discrepancy)
- formerly_proven 4y ago
  The first CCD is binned for the SKU's spec, the other is whatever. This has been true for all chiplet Ryzens. Though the effect used to be more extreme, I had for example a 3900X where the second CCD only managed to run at 4.1 GHz under load, compared to ~4.4 GHz on the first CCD (and 4.6 GHz being printed on the box). That's pretty common with those.
- xattt 4y ago
  Is there optimization being done by AMD to locate the best performing chiplet on the best possible place on the bus?
  - wmf 4y ago
    There's no bus and thus no place on the bus.
DiabloD3 4y ago
?950x chips in particular are binned that way, the first die is an "Epyc"-grade bin, the second die is a bin good enough for ?800x (or, if sold as 6 cores, both of the ?900x cores). AMD binning independently works of functioning cores; having all 8 cores working does not mean it magically bins higher. AMD has not commented publicly on this, but it is generally believed there are two Epyc bins (one for high perf, one for low voltage, both exceptional quality), one high quality Ryzen bin, and one low quality bin. ?950x contains one Epyc quality + one high quality; x models contain high quality dies (in addition to being binned for broken cores in 6 core-based models independent of clock speed binning), non-x using lower quality dies. Threadrippers are bin-selected similarly to ?950xs. All 6 core Zen 2 chips that were sold were 3+3, never 4+2/2+4. The only exception to the above binning is a single 4 core non-APU Zen 2 existed, using the very few dies where an entire CCX was dead in the CCD, but the other CCX worked. This also mean half the L3 was dead (as the L3 was split per CCX, and wasn't CCD wide). With Zen 3 and 4, this chip can't exist as they are single CCX (all 8 cores) per CCD. Die binning, however, isn't magical. ?800x record-setting overclocks are only a smidgen behind record-setting ?590x per-chiplet overclocks.
alberth 4y ago
Thermos? Could it be a simpler explanation in that the thermos of cores 1 & 4 are better than where other cores are located?

by jagrsw 4y ago

Rarebox 4y ago

This would make sense right? You probably can't run all cores at max turbo frequency before hitting power and thermal limits. So dividing chiplets based on binning would result in good performance for 1-8 -threaded tasks while reducing chip lottery. (But it's possible there are other reasons for the discrepancy)

formerly_proven 4y ago
The first CCD is binned for the SKU's spec, the other is whatever. This has been true for all chiplet Ryzens. Though the effect used to be more extreme, I had for example a 3900X where the second CCD only managed to run at 4.1 GHz under load, compared to ~4.4 GHz on the first CCD (and 4.6 GHz being printed on the box). That's pretty common with those.
xattt 4y ago
Is there optimization being done by AMD to locate the best performing chiplet on the best possible place on the bus?
- wmf 4y ago
  There's no bus and thus no place on the bus.

DiabloD3 4y ago

?950x chips in particular are binned that way, the first die is an "Epyc"-grade bin, the second die is a bin good enough for ?800x (or, if sold as 6 cores, both of the ?900x cores). AMD binning independently works of functioning cores; having all 8 cores working does not mean it magically bins higher. AMD has not commented publicly on this, but it is generally believed there are two Epyc bins (one for high perf, one for low voltage, both exceptional quality), one high quality Ryzen bin, and one low quality bin. ?950x contains one Epyc quality + one high quality; x models contain high quality dies (in addition to being binned for broken cores in 6 core-based models independent of clock speed binning), non-x using lower quality dies. Threadrippers are bin-selected similarly to ?950xs. All 6 core Zen 2 chips that were sold were 3+3, never 4+2/2+4. The only exception to the above binning is a single 4 core non-APU Zen 2 existed, using the very few dies where an entire CCX was dead in the CCD, but the other CCX worked. This also mean half the L3 was dead (as the L3 was split per CCX, and wasn't CCD wide). With Zen 3 and 4, this chip can't exist as they are single CCX (all 8 cores) per CCD. Die binning, however, isn't magical. ?800x record-setting overclocks are only a smidgen behind record-setting ?590x per-chiplet overclocks.

alberth 4y ago

Thermos? Could it be a simpler explanation in that the thermos of cores 1 & 4 are better than where other cores are located?