2 ms·

Interesting final point. Makes me think that a solution to the apparent crisis around Moore's law may be to break up monolithic super-chips into smaller co-proc

by uoaei 4y ago

Interesting final point. Makes me think that a solution to the apparent crisis around Moore's law may be to break up monolithic super-chips into smaller co-processors. This would help alleviate the bottleneck of waste heat management that apparently these mega-chips seem to be getting throttled by. This is already being done for other reasons, but mitigating the volume-to-surface-area ratio extremes of large chips may have second-order benefits for computing performance.

dragontamer 4y ago
> This would help alleviate the bottleneck of waste heat management that apparently these mega-chips seem to be getting throttled by. The opposite. A lot of these chips are being designed as "dark silicon", with extremely specific hardware that is rarely used. When the silicon is dark, they form a heatsink that can absorb excess heat from all other parts of the chip and help regulate the temperature. I expect more-and-more extremely specific circuitry to be added to future chips, so that more and more silicon can be "dark" and serve as a place for heat to go inside of the microseconds of execution.
- nine_k 4y ago
  Agreed. Most whole cores on most consumer CPUs are idle, or close to idle. much / most of the time. The big-little architecture is built around the idea of large cores idling / shut down most of the time, and only waking up to serve a peak load, e.g. when a new web page is being rendered. I an even imagine spacing functional nodes wider on the silicon, where size and latency limitations allow, to give them more heat-dissipating area.
  - rbanffy 4y ago
    > The big-little architecture is built around the idea of large cores idling / shut down most of the time, and only waking up to serve a peak load This would suggest placing E cores between (or even inside) P cores, every cluster of them maybe on a small chiplet. I wonder if the idea could go as far as having efficient and performant execution units in the same processor, with the reorder buffer issuing instructions to different units according to how far down the instruction stream the result is needed.

by uoaei 4y ago

dragontamer 4y ago

> This would help alleviate the bottleneck of waste heat management that apparently these mega-chips seem to be getting throttled by. The opposite. A lot of these chips are being designed as "dark silicon", with extremely specific hardware that is rarely used. When the silicon is dark, they form a heatsink that can absorb excess heat from all other parts of the chip and help regulate the temperature. I expect more-and-more extremely specific circuitry to be added to future chips, so that more and more silicon can be "dark" and serve as a place for heat to go inside of the microseconds of execution.

nine_k 4y ago
Agreed. Most whole cores on most consumer CPUs are idle, or close to idle. much / most of the time. The big-little architecture is built around the idea of large cores idling / shut down most of the time, and only waking up to serve a peak load, e.g. when a new web page is being rendered. I an even imagine spacing functional nodes wider on the silicon, where size and latency limitations allow, to give them more heat-dissipating area.
- rbanffy 4y ago
  > The big-little architecture is built around the idea of large cores idling / shut down most of the time, and only waking up to serve a peak load This would suggest placing E cores between (or even inside) P cores, every cluster of them maybe on a small chiplet. I wonder if the idea could go as far as having efficient and performant execution units in the same processor, with the reorder buffer issuing instructions to different units according to how far down the instruction stream the result is needed.