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M1 is a bigger core than any other core I know of. Just larger reorder buffers, wider execution, etc. etc. Nominally speaking, its inefficient at that point. Y

M1 is a bigger core than any other core I know of. Just larger reorder buffers, wider execution, etc. etc. Nominally speaking, its inefficient at that point. You pretty much can make 2 cores fit inside of the M1 core, and each x86 core supports two threads (Would you rather have 4x x86 threads, or 1x M1 core??). I'm intrigued that people continue to find benefits from such a large core (even without SMT / Hyperthreading). -------- But yes, M1 has huge L1 cache, huge reorder buffers, and extremely wide execution. I'd expect it to win clock-for-clock vs any other core in the market. But I'm not fully convinced that its the best design / tradeoff. Intel's E-cores + P-cores suggests that modern CPU cores may have become overly big.

smachiz 4y ago
You're comparing apples and oranges to an extent - the M1/M2 delivery like.... 5x the performance per watt of x86 designs. Even the E-cores draw more power than the M1/M2 cores.
- dragontamer 4y ago
  Not really. You can always cut down power consumption by running them slower GHz. Among other tricks. As far as I'm aware, AMD EPYC continues to win performance/watt crown in practical server applications (servers also cut down on GHz to try to keep things power-efficient. Better to have many cores at lower GHz to win power-efficiency races). The interesting thing to me is die-area. Because that's what determines how many cores you get per chip.
  - xenadu02 4y ago
    > Not really. You can always cut down power consumption by running them slower GHz But that ruins the original argument... Not that any amount of down clocking can let Intel or AMD get close on the perf/power graph. Besides heat is the main bottleneck on data center density and operational cost. This is the denialist argument I keep seeing where people want to have their cake and eat it (or perpetually pin their hopes on Zen+1 that hasn't actually shipped). If Intel could match M1/M2 power/perf they'd do it. But they can't. They can win the perf crown by absolutely burning power or they can get massively trounced to kinda get close on power. Zen is better but still has the same fundamental trade off. Instead of saying M1/M2 are nothing special I'm super excited to see actual competition in the CPU space for the first time in a long time - competition that has proven a lot of conventional wisdom to be bunk.
    - zozbot234 4y ago
      But is it real competition at the μarch level or just a more advanced fabrication process being used? We have yet to see x86 chips on the same process as the Apple M1 or M2.
    - dragontamer 4y ago
      > This is the denialist argument ??? My argument is, look at server power/performance. AMD EPYC takes the crown. 80-core ARM does not. Maybe M1 will win, but we've at best got like 8 cores right now. As I stated earlier: M1 cores are huge. I'm not convinced they're better yet, but if Apple wants to make a 32-core M1 or M2 and compare it to an AMD EPYC 64x2 computer, that's when I'll start looking. We will see what they can do moving forward, but I don't expect that this M1 core can scale to a manycore size like EPYC (or Xeon, to a lesser extent). Benchmarks are always crap, but they're the best we've got. Benchmarks, for now, show that Dual EPYC still is your best computer. At least for the server-scale that Supermicro operates at. ------- ARM themselves are keen on this. ARM has V, N, and E cores moving forward because they're heading their bets. This Supermicro system is probably an N2 or N1 system? (I haven't looked into it much). No one else in the world is making cores as large as Apple's M1. Its an aberration, abnormally huge. If Apple fans find it useful then cool but there's other workloads out here. I'm not fully convinced that such a large core like M1 is the best design.
    - ipsum2 4y ago
      Actually, Intel beats M1/M2 in perf/watt benchmarks: https://www.cpubenchmark.net/power_performance.html https://www.cpubenchmark.net/power_performance.html
      - sliken 4y ago
        Very weird measure of efficiency. Perf/(Max TDP) doesn't really measure efficiency. Running a workload you care about and measure power usage at the wall would be a MUCH better metric. The Intel chip might well spend most of it's time at Max TDP and throttling while the M1 might require unusual circumstances (like maxing out the fast cores, slow cores, matrix multiply (which is outside the core), memory controller, and iGPU simultaneously. There's not really any way to tell from the posted benchmark. Wonder if the i7-1250 runs in any laptops without a fan.
  - jjtheblunt 4y ago
    > ...die area. Because that's what determines how many cores you get per chip the process (3nm, ...) too, to get a sense of what fits in an area
- idkyall 4y ago
  >Even the E-cores draw more power than the M1/M2 cores. To be clear, this is also a product of the fabrication process and node size. Intel 12/13th gen are on Intel 7[1] - which is fairly old at this point, while M1s are fabricated on 5mm process[2]. Smaller lithography size isn't the whole story, but it certainly does make a difference [1]https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros https://www.anandtech.com/show/16823/intel-accelerated-offen... [2] https://wccftech.com/apple-5nm-m1-chip-for-arm-macs-2x-performance/ https://wccftech.com/apple-5nm-m1-chip-for-arm-macs-2x-perfo...
  - dragontamer 4y ago
    To be fair: Intel 10 years ago would always lean on its manufacturing advantage for why its chips were better than everyone else's. Today, TSMC has taken the lead, and Apple pays the big bucks to be a prioritized customer above all others.
toast0 4y ago
Apple is designing for more IPC and lower clocks, whereas Intel and AMD basically need to target their designs towards a 5GHz target clock rate to remain competitive in the marketplace. A lower clocked, but much wider core can be much more power efficient, and Apple almost never provided sufficient cooling to run Intel processors at sustained top speeds anyway. A larger die increases cost, but vertical integration means you don't have to find margin on each component, just the assembled product. E cores work the problem the other way, if you narrow the core, you can get about half the work done per core, but in about a fourth the space. That's a win for throughput, but not for latency/interactivity. Drastically different per core performance makes OS schedulers work harder though.
- zozbot234 4y ago
  Why can't you use E-cores for better latency and interactivity? Unless you're doing heavy-duty VR or video gaming, you don't ever need more than a single efficiency thread to run your UX. Just need to avoid doing any real workload on the UI thread.
  - toast0 4y ago
    A P-core is going to give you better latency than an E-core, because it does the work twice as fast. Yes, if you can split the work, you can get it done faster with 4 Es than one P, but lots of interactive work is hard to split. You can't meaningfully handle a network interrupt with more than one core; you can split your network interface into multiple queues and service each queue with a separate core, but parallelizing within the queue only brings sadness and cache coherency latency. You might get some interactivity benefits depending on your workload and core configuration... One P vs 4 Es is an easy choice, but 4-P vs 16-E, the 4-P is probably going to feel more interactive because UI latency is lower, even though throughput is lower.
uoaei 4y ago
Interesting final point. Makes me think that a solution to the apparent crisis around Moore's law may be to break up monolithic super-chips into smaller co-processors. This would help alleviate the bottleneck of waste heat management that apparently these mega-chips seem to be getting throttled by. This is already being done for other reasons, but mitigating the volume-to-surface-area ratio extremes of large chips may have second-order benefits for computing performance.
- dragontamer 4y ago
  > This would help alleviate the bottleneck of waste heat management that apparently these mega-chips seem to be getting throttled by. The opposite. A lot of these chips are being designed as "dark silicon", with extremely specific hardware that is rarely used. When the silicon is dark, they form a heatsink that can absorb excess heat from all other parts of the chip and help regulate the temperature. I expect more-and-more extremely specific circuitry to be added to future chips, so that more and more silicon can be "dark" and serve as a place for heat to go inside of the microseconds of execution.
  - nine_k 4y ago
    Agreed. Most whole cores on most consumer CPUs are idle, or close to idle. much / most of the time. The big-little architecture is built around the idea of large cores idling / shut down most of the time, and only waking up to serve a peak load, e.g. when a new web page is being rendered. I an even imagine spacing functional nodes wider on the silicon, where size and latency limitations allow, to give them more heat-dissipating area.
    - rbanffy 4y ago
      > The big-little architecture is built around the idea of large cores idling / shut down most of the time, and only waking up to serve a peak load This would suggest placing E cores between (or even inside) P cores, every cluster of them maybe on a small chiplet. I wonder if the idea could go as far as having efficient and performant execution units in the same processor, with the reorder buffer issuing instructions to different units according to how far down the instruction stream the result is needed.
rbanffy 4y ago
> M1 has huge L1 cache, huge reorder buffers At first I thought it would be the close integration of memory, but it seems the consistent instruction size makes the reorder buffers a lot simpler to implement than for x86, so you can get a much larger aarch64 reorder buffer for the same area of an x86 (amd64) one.
- dragontamer 4y ago
  I think you might have your wires crossed a bit. A ROB / Reorder Buffer is just RAM from my understanding. Since writes are all out of order, the ROB holds the "future values" of things for sections of code that have already executed (due to out-of-order scheduling), that are waiting for "earlier" code to execute. Ex: If line#105 has been out-of-order executed, and knows that "MemoryLocationX = 100" happens there... the ROB holds it until line#90 through line#014 are done executing. ----------------- Consistent instruction size would decrease: * uop cache (AMD / Intel require a uop cache, where "decoded" instructions stay). This is more optional for ARM... and I'd personally expect this to be the "biggest cost" of x86 instructions. * Decoder (due to the complexity of x86 instructions, the decoder on those chips is probably bigger). The ROB / Reorder buffer is "after the decoder", probably just interacting with uops directly. I doubt that instruction set size-or-complexity has anything to do with ROB sizes.
  - deleted 4y ago
    [deleted]
brigade 4y ago
Area-wise I'm pretty sure Apple's P-cores are in line with Intel and AMD - including L2 cache and other shared logic, M1's P-core was 4mm^2 per core, M2's P-core is about 5mm^2 [1], Zen 3 and 4 were about 4mm^2 [2], and Intel is 7mm^2 for Golden Cove [3] [1] https://www.semianalysis.com/p/apple-m2-die-shot-and-architecture https://www.semianalysis.com/p/apple-m2-die-shot-and-archite... [2] https://www.hwcooling.net/en/zen-4-architecture-chip-parameters-and-ipc-of-amds-new-core/ https://www.hwcooling.net/en/zen-4-architecture-chip-paramet... [3] https://twitter.com/locuza_/status/1453524285260247046 https://twitter.com/locuza_/status/1453524285260247046
- dragontamer 4y ago
  M2 P-core is 5mm^2 on 3nm process. Zen3 is 4mm^2 on 7nm process... a process that uses 4x the area per transistor than the 3nm process.
  - brigade 4y ago
    M1, M2, and Zen 4 are all on TSMC 5nm TSMC only just started mass production of 3nm like last week, nothing has shipped yet.
    - dragontamer 4y ago
      Most of the benchmarks I'm familiar with are M1/M2 vs Zen3. I don't think people have comprehensively tested Zen4 yet. Zen3 was 7nm for sure. So AMD Zen3 ~4mm^2 on 7nm is ~364 million transistors, while Apple's ~5mm^2 on 5nm is ~856 million transistors (https://en.wikichip.org/wiki/File:5nm_densities.svg https://en.wikichip.org/wiki/File:5nm_densities.svg). With M1/M2 in the ~5mm^2 area or so, I definitely argue that Zen3 cores are 1/2 the size of M1/M2 cores, transistor-for-transistor. Its a fat core. Maybe it will work thanks to how advanced processes are getting. Maybe this will encourage others (ie: Intel) to experiment with larger cores as well. Its hard for me to say, but I do welcome the benchmarks.
      - brigade 4y ago

smachiz 4y ago

You're comparing apples and oranges to an extent - the M1/M2 delivery like.... 5x the performance per watt of x86 designs. Even the E-cores draw more power than the M1/M2 cores.

dragontamer 4y ago
Not really. You can always cut down power consumption by running them slower GHz. Among other tricks. As far as I'm aware, AMD EPYC continues to win performance/watt crown in practical server applications (servers also cut down on GHz to try to keep things power-efficient. Better to have many cores at lower GHz to win power-efficiency races). The interesting thing to me is die-area. Because that's what determines how many cores you get per chip.
- xenadu02 4y ago
  > Not really. You can always cut down power consumption by running them slower GHz But that ruins the original argument... Not that any amount of down clocking can let Intel or AMD get close on the perf/power graph. Besides heat is the main bottleneck on data center density and operational cost. This is the denialist argument I keep seeing where people want to have their cake and eat it (or perpetually pin their hopes on Zen+1 that hasn't actually shipped). If Intel could match M1/M2 power/perf they'd do it. But they can't. They can win the perf crown by absolutely burning power or they can get massively trounced to kinda get close on power. Zen is better but still has the same fundamental trade off. Instead of saying M1/M2 are nothing special I'm super excited to see actual competition in the CPU space for the first time in a long time - competition that has proven a lot of conventional wisdom to be bunk.
  - zozbot234 4y ago
    But is it real competition at the μarch level or just a more advanced fabrication process being used? We have yet to see x86 chips on the same process as the Apple M1 or M2.
  - dragontamer 4y ago
    > This is the denialist argument ??? My argument is, look at server power/performance. AMD EPYC takes the crown. 80-core ARM does not. Maybe M1 will win, but we've at best got like 8 cores right now. As I stated earlier: M1 cores are huge. I'm not convinced they're better yet, but if Apple wants to make a 32-core M1 or M2 and compare it to an AMD EPYC 64x2 computer, that's when I'll start looking. We will see what they can do moving forward, but I don't expect that this M1 core can scale to a manycore size like EPYC (or Xeon, to a lesser extent). Benchmarks are always crap, but they're the best we've got. Benchmarks, for now, show that Dual EPYC still is your best computer. At least for the server-scale that Supermicro operates at. ------- ARM themselves are keen on this. ARM has V, N, and E cores moving forward because they're heading their bets. This Supermicro system is probably an N2 or N1 system? (I haven't looked into it much). No one else in the world is making cores as large as Apple's M1. Its an aberration, abnormally huge. If Apple fans find it useful then cool but there's other workloads out here. I'm not fully convinced that such a large core like M1 is the best design.
  - ipsum2 4y ago
    Actually, Intel beats M1/M2 in perf/watt benchmarks: https://www.cpubenchmark.net/power_performance.html https://www.cpubenchmark.net/power_performance.html
    - sliken 4y ago
      Very weird measure of efficiency. Perf/(Max TDP) doesn't really measure efficiency. Running a workload you care about and measure power usage at the wall would be a MUCH better metric. The Intel chip might well spend most of it's time at Max TDP and throttling while the M1 might require unusual circumstances (like maxing out the fast cores, slow cores, matrix multiply (which is outside the core), memory controller, and iGPU simultaneously. There's not really any way to tell from the posted benchmark. Wonder if the i7-1250 runs in any laptops without a fan.
- jjtheblunt 4y ago
  > ...die area. Because that's what determines how many cores you get per chip the process (3nm, ...) too, to get a sense of what fits in an area
idkyall 4y ago
>Even the E-cores draw more power than the M1/M2 cores. To be clear, this is also a product of the fabrication process and node size. Intel 12/13th gen are on Intel 7[1] - which is fairly old at this point, while M1s are fabricated on 5mm process[2]. Smaller lithography size isn't the whole story, but it certainly does make a difference [1]https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros https://www.anandtech.com/show/16823/intel-accelerated-offen... [2] https://wccftech.com/apple-5nm-m1-chip-for-arm-macs-2x-performance/ https://wccftech.com/apple-5nm-m1-chip-for-arm-macs-2x-perfo...
- dragontamer 4y ago
  To be fair: Intel 10 years ago would always lean on its manufacturing advantage for why its chips were better than everyone else's. Today, TSMC has taken the lead, and Apple pays the big bucks to be a prioritized customer above all others.

toast0 4y ago

Apple is designing for more IPC and lower clocks, whereas Intel and AMD basically need to target their designs towards a 5GHz target clock rate to remain competitive in the marketplace. A lower clocked, but much wider core can be much more power efficient, and Apple almost never provided sufficient cooling to run Intel processors at sustained top speeds anyway. A larger die increases cost, but vertical integration means you don't have to find margin on each component, just the assembled product. E cores work the problem the other way, if you narrow the core, you can get about half the work done per core, but in about a fourth the space. That's a win for throughput, but not for latency/interactivity. Drastically different per core performance makes OS schedulers work harder though.

zozbot234 4y ago
Why can't you use E-cores for better latency and interactivity? Unless you're doing heavy-duty VR or video gaming, you don't ever need more than a single efficiency thread to run your UX. Just need to avoid doing any real workload on the UI thread.
- toast0 4y ago
  A P-core is going to give you better latency than an E-core, because it does the work twice as fast. Yes, if you can split the work, you can get it done faster with 4 Es than one P, but lots of interactive work is hard to split. You can't meaningfully handle a network interrupt with more than one core; you can split your network interface into multiple queues and service each queue with a separate core, but parallelizing within the queue only brings sadness and cache coherency latency. You might get some interactivity benefits depending on your workload and core configuration... One P vs 4 Es is an easy choice, but 4-P vs 16-E, the 4-P is probably going to feel more interactive because UI latency is lower, even though throughput is lower.

uoaei 4y ago

Interesting final point. Makes me think that a solution to the apparent crisis around Moore's law may be to break up monolithic super-chips into smaller co-processors. This would help alleviate the bottleneck of waste heat management that apparently these mega-chips seem to be getting throttled by. This is already being done for other reasons, but mitigating the volume-to-surface-area ratio extremes of large chips may have second-order benefits for computing performance.

dragontamer 4y ago
> This would help alleviate the bottleneck of waste heat management that apparently these mega-chips seem to be getting throttled by. The opposite. A lot of these chips are being designed as "dark silicon", with extremely specific hardware that is rarely used. When the silicon is dark, they form a heatsink that can absorb excess heat from all other parts of the chip and help regulate the temperature. I expect more-and-more extremely specific circuitry to be added to future chips, so that more and more silicon can be "dark" and serve as a place for heat to go inside of the microseconds of execution.
- nine_k 4y ago
  Agreed. Most whole cores on most consumer CPUs are idle, or close to idle. much / most of the time. The big-little architecture is built around the idea of large cores idling / shut down most of the time, and only waking up to serve a peak load, e.g. when a new web page is being rendered. I an even imagine spacing functional nodes wider on the silicon, where size and latency limitations allow, to give them more heat-dissipating area.
  - rbanffy 4y ago
    > The big-little architecture is built around the idea of large cores idling / shut down most of the time, and only waking up to serve a peak load This would suggest placing E cores between (or even inside) P cores, every cluster of them maybe on a small chiplet. I wonder if the idea could go as far as having efficient and performant execution units in the same processor, with the reorder buffer issuing instructions to different units according to how far down the instruction stream the result is needed.

rbanffy 4y ago

> M1 has huge L1 cache, huge reorder buffers At first I thought it would be the close integration of memory, but it seems the consistent instruction size makes the reorder buffers a lot simpler to implement than for x86, so you can get a much larger aarch64 reorder buffer for the same area of an x86 (amd64) one.

dragontamer 4y ago
I think you might have your wires crossed a bit. A ROB / Reorder Buffer is just RAM from my understanding. Since writes are all out of order, the ROB holds the "future values" of things for sections of code that have already executed (due to out-of-order scheduling), that are waiting for "earlier" code to execute. Ex: If line#105 has been out-of-order executed, and knows that "MemoryLocationX = 100" happens there... the ROB holds it until line#90 through line#014 are done executing. ----------------- Consistent instruction size would decrease: * uop cache (AMD / Intel require a uop cache, where "decoded" instructions stay). This is more optional for ARM... and I'd personally expect this to be the "biggest cost" of x86 instructions. * Decoder (due to the complexity of x86 instructions, the decoder on those chips is probably bigger). The ROB / Reorder buffer is "after the decoder", probably just interacting with uops directly. I doubt that instruction set size-or-complexity has anything to do with ROB sizes.
- deleted 4y ago
  [deleted]

brigade 4y ago

Area-wise I'm pretty sure Apple's P-cores are in line with Intel and AMD - including L2 cache and other shared logic, M1's P-core was 4mm^2 per core, M2's P-core is about 5mm^2 [1], Zen 3 and 4 were about 4mm^2 [2], and Intel is 7mm^2 for Golden Cove [3] [1] https://www.semianalysis.com/p/apple-m2-die-shot-and-architecture https://www.semianalysis.com/p/apple-m2-die-shot-and-archite... [2] https://www.hwcooling.net/en/zen-4-architecture-chip-parameters-and-ipc-of-amds-new-core/ https://www.hwcooling.net/en/zen-4-architecture-chip-paramet... [3] https://twitter.com/locuza_/status/1453524285260247046 https://twitter.com/locuza_/status/1453524285260247046

dragontamer 4y ago
M2 P-core is 5mm^2 on 3nm process. Zen3 is 4mm^2 on 7nm process... a process that uses 4x the area per transistor than the 3nm process.
- brigade 4y ago
  M1, M2, and Zen 4 are all on TSMC 5nm TSMC only just started mass production of 3nm like last week, nothing has shipped yet.
  - dragontamer 4y ago
    Most of the benchmarks I'm familiar with are M1/M2 vs Zen3. I don't think people have comprehensively tested Zen4 yet. Zen3 was 7nm for sure. So AMD Zen3 ~4mm^2 on 7nm is ~364 million transistors, while Apple's ~5mm^2 on 5nm is ~856 million transistors (https://en.wikichip.org/wiki/File:5nm_densities.svg https://en.wikichip.org/wiki/File:5nm_densities.svg). With M1/M2 in the ~5mm^2 area or so, I definitely argue that Zen3 cores are 1/2 the size of M1/M2 cores, transistor-for-transistor. Its a fat core. Maybe it will work thanks to how advanced processes are getting. Maybe this will encourage others (ie: Intel) to experiment with larger cores as well. Its hard for me to say, but I do welcome the benchmarks.
    - brigade 4y ago