5 ms·

Does this account for the ubiquitous riscv compression extension?

by photonbeam 4y ago

inkyoto 4y ago
The compression extension is RISC-V 32-bit. All code has been compiled for 64-bit architectures for a comparison.
- ansible 4y ago
  That is not correct. Compressed instructions are available for 32-bit (RV32) and 64-bit (RV64). The compressed instructions differ slightly between the two though. See my other comment in this thread.
  - inkyoto 4y ago
    I am more than happy to stand corrected, if a correction is warranted. What is the gcc 12.2.0 -march= value to make gcc 12.2.0 emit the compressed 64-bit code? The gcc 12.2.0 rejects all the -march RISC-V values the gcc documentation cites, e.g. rv64i is not accepted, and it is documented. I had presumed it was -march=rv64Zc[…], with […] being a combination of a/b/c/d/f/cmp/cmt, and neither of those was accepted. Also, according to https://wiki.riscv.org/display/HOME/Specification+Status https://wiki.riscv.org/display/HOME/Specification+Status, code size extensions are in a review state slated for a ratification in Q1 2023, with «ABI issues being worked» mentioned in the notes. My interpretation is that the compressed instructions extension is still work in progress, and is a moot point to discuss at this very moment.
    - cesarb 4y ago
      > My interpretation is that the compressed instructions extension is still work in progress, and is a moot point to discuss at this very moment. The compressed instructions extension (the C extension) has been finished and standardized for a long time. In fact, all mainstream desktop Linux distributions which have ported to RISC-V have standardized on RV64GC (aka RV64IMAFDC, with the extensions I, M, A, F, D, C), that is, they require compressed instructions.
      - inkyoto 4y ago
        So what is the gcc (or gas via gcc) compiler switch to make the RISC-V compiler backend yiled compressed instructions? I have been unable to find a working one in the documentation, and the beehive mind has been of no help either.
        ansible 4y ago
        Compressed instructions are generated by default with recent versions of GCC for RV64GC and RV32GC.
    - snvzz 4y ago
      >My interpretation is that the compressed instructions extension is still work in progress C was ratified years ago, but I suspect you might have heard about Zc (about to be ratified, specific to 32bit, particularly helpful to microcontrollers) or B (ratified recently, bit manipulation, happens to help code density), and their effect in code density.
ansible 4y ago
Yes and no. The GP is counting instructions, which is approximately the same between ARM64 and RV64. Others are talking about code density where RISC-V currently has a significant advantage due to compressed instructions. ----------------- For the above code segment, though I selected the compile-to-binary option, and the program failed to compile. So I don't know what's up with that. On a relatively short chunk of C++ code, you can see the compressed (16-bit) instructions in the binary output: https://godbolt.org/z/jzjzrrfMP https://godbolt.org/z/jzjzrrfMP Some instructions, such as the ones with a larger immediate load, are 32-bit. Same version of GCC / G++ as the above. The actual code size of the ARM64 is bigger: https://godbolt.org/z/Wq7jKz5rY https://godbolt.org/z/Wq7jKz5rY I'm not sure why all the NOP instructions are in there, but even discounting that, all the generated machine instructions are 32-bit. Is there another option for GCC that will help? Or am I mistaken in thinking there is a Thumb2 equivalent for this target? Edit: Answer: No. A64 is fixed-length: https://developer.arm.com/documentation/den0024/a/An-Introduction-to-the-ARMv8-Instruction-Sets/The-ARMv8-instruction-sets https://developer.arm.com/documentation/den0024/a/An-Introdu...
- inkyoto 4y ago
  For the sake of savouring a civilised nerdy discourse, may we stick to the same code and set a rule that only compiler switches can be fiddled with? Comparing 3 lines (after discarding empty lines, curly braces, functions and variable declarations) of unrelated code (which is not a C++ code anyway) yielding a 5 or so CPU instructions is boring and is not enlightening in our quest to reveal the light and unveil the path to truth. The piece of C++ code I have uploaded to GodBolt was floated on HN a few years ago as an instance of the template metaprograaming that crashed one C++ compiler and resulted in an OOM process kill for another (for the record, it was clang++ and g++ although I can't remember which one did what). Both compilers have been fixed since then, but the code is still interesting due to it being: a) terse, and b) resulting in a unusually large number of [mostly useless] numeric computations that a C++ compiler yields by virtue of the template expansion. So I have retained a copy of the mischievous code. The template expansion is common in C++ template metaprogramming, and is extensively used in C++ scientific libraries (e.g. BLASS as well as in others). When it comes to the generated code footprint comparison, the numeric computations are a good metric to assess.

Does this account for the ubiquitous riscv compression extension?

inkyoto 4y ago

The compression extension is RISC-V 32-bit. All code has been compiled for 64-bit architectures for a comparison.

ansible 4y ago
That is not correct. Compressed instructions are available for 32-bit (RV32) and 64-bit (RV64). The compressed instructions differ slightly between the two though. See my other comment in this thread.
- inkyoto 4y ago
  I am more than happy to stand corrected, if a correction is warranted. What is the gcc 12.2.0 -march= value to make gcc 12.2.0 emit the compressed 64-bit code? The gcc 12.2.0 rejects all the -march RISC-V values the gcc documentation cites, e.g. rv64i is not accepted, and it is documented. I had presumed it was -march=rv64Zc[…], with […] being a combination of a/b/c/d/f/cmp/cmt, and neither of those was accepted. Also, according to https://wiki.riscv.org/display/HOME/Specification+Status https://wiki.riscv.org/display/HOME/Specification+Status, code size extensions are in a review state slated for a ratification in Q1 2023, with «ABI issues being worked» mentioned in the notes. My interpretation is that the compressed instructions extension is still work in progress, and is a moot point to discuss at this very moment.
  - cesarb 4y ago
    > My interpretation is that the compressed instructions extension is still work in progress, and is a moot point to discuss at this very moment. The compressed instructions extension (the C extension) has been finished and standardized for a long time. In fact, all mainstream desktop Linux distributions which have ported to RISC-V have standardized on RV64GC (aka RV64IMAFDC, with the extensions I, M, A, F, D, C), that is, they require compressed instructions.
    - inkyoto 4y ago
      So what is the gcc (or gas via gcc) compiler switch to make the RISC-V compiler backend yiled compressed instructions? I have been unable to find a working one in the documentation, and the beehive mind has been of no help either.
      - ansible 4y ago
        Compressed instructions are generated by default with recent versions of GCC for RV64GC and RV32GC.
  - snvzz 4y ago
    >My interpretation is that the compressed instructions extension is still work in progress C was ratified years ago, but I suspect you might have heard about Zc (about to be ratified, specific to 32bit, particularly helpful to microcontrollers) or B (ratified recently, bit manipulation, happens to help code density), and their effect in code density.

ansible 4y ago

Yes and no. The GP is counting instructions, which is approximately the same between ARM64 and RV64. Others are talking about code density where RISC-V currently has a significant advantage due to compressed instructions. ----------------- For the above code segment, though I selected the compile-to-binary option, and the program failed to compile. So I don't know what's up with that. On a relatively short chunk of C++ code, you can see the compressed (16-bit) instructions in the binary output: https://godbolt.org/z/jzjzrrfMP https://godbolt.org/z/jzjzrrfMP Some instructions, such as the ones with a larger immediate load, are 32-bit. Same version of GCC / G++ as the above. The actual code size of the ARM64 is bigger: https://godbolt.org/z/Wq7jKz5rY https://godbolt.org/z/Wq7jKz5rY I'm not sure why all the NOP instructions are in there, but even discounting that, all the generated machine instructions are 32-bit. Is there another option for GCC that will help? Or am I mistaken in thinking there is a Thumb2 equivalent for this target? Edit: Answer: No. A64 is fixed-length: https://developer.arm.com/documentation/den0024/a/An-Introduction-to-the-ARMv8-Instruction-Sets/The-ARMv8-instruction-sets https://developer.arm.com/documentation/den0024/a/An-Introdu...

inkyoto 4y ago
For the sake of savouring a civilised nerdy discourse, may we stick to the same code and set a rule that only compiler switches can be fiddled with? Comparing 3 lines (after discarding empty lines, curly braces, functions and variable declarations) of unrelated code (which is not a C++ code anyway) yielding a 5 or so CPU instructions is boring and is not enlightening in our quest to reveal the light and unveil the path to truth. The piece of C++ code I have uploaded to GodBolt was floated on HN a few years ago as an instance of the template metaprograaming that crashed one C++ compiler and resulted in an OOM process kill for another (for the record, it was clang++ and g++ although I can't remember which one did what). Both compilers have been fixed since then, but the code is still interesting due to it being: a) terse, and b) resulting in a unusually large number of [mostly useless] numeric computations that a C++ compiler yields by virtue of the template expansion. So I have retained a copy of the mischievous code. The template expansion is common in C++ template metaprogramming, and is extensively used in C++ scientific libraries (e.g. BLASS as well as in others). When it comes to the generated code footprint comparison, the numeric computations are a good metric to assess.