27 ms·
The project was this: http://retroramblings.net/?page_id=1339 http://retroramblings.net/?page_id=1339 I ended up using a fixed instruction width of 8 bits, with
by robinsonb5 4y ago
The project was this: http://retroramblings.net/?page_id=1339 http://retroramblings.net/?page_id=1339
I ended up using a fixed instruction width of 8 bits, with eight classical registers (one of which is the program counter), and also a "temp" register which is used implicitly for opcodes which need a second operand.
The code density is comparable to m68k and x86, better than 32-bit RISC ISAs, but not as good as the 16-bit compressed representations of 32-bit RISC ISAs.
- klelatti 4y agoThanks so much! Looks like a really great project. I'll have a full look through the blog later but just the summary of the code density results is very interesting (at http://retroramblings.net/?p=1414 http://retroramblings.net/?p=1414). Do you have a gut feel for what is happening here and why the compressed 32 RISC ISAs do so well compared to yours?
- robinsonb5 4y agoI think there are three reasons: one is that the code my compiler backend produces is "ok" but not fantastic (though it's somewhat better now than it was when that article was written) - another is that I have only 8 registers, and only five are available for the code generator to play with, so I have to spill registers onto the stack sooner than more register-rich ISAs - and finally my simplistic 8-bit instructions don't do as much as a RISC ISA's 16-bit instructions, so some of the advantage of them being only a single byte is lost.
- klelatti 4y agoThat makes a lot of sense. Thanks again for sharing such an interesting project.