There are plenty of "invalid addresses" in DDR5 before this. All existing DDR5 modules regardless of size use the same command and addressing scheme, which allo

There are plenty of "invalid addresses" in DDR5 before this. All existing DDR5 modules regardless of size use the same command and addressing scheme, which allows for 3-bit chip id, 3-bit bank group id, 2-bit bank id, 16-bit row address and 7-bit column address. [0] This, combined with the 8-bit minimum burst (and ability to only address at 8-bit granularity), means that every single normal x64 DDR5 module has an "address space" of 256GB. Any modules smaller than that do not implement all of the features of the addressing system and the memory controller has to query them beforehand to find out which parts are implemented, and so which addresses are safe to use. (Different modules might use different parts of the system -- as in, modules of the same capacity implemented with older manufacturing tech might use more chipid bits and less row address bits or bank groups.) In no way is every possible pointer a word you can address. [0]: and one as of yet unimplemented additional reserved bit for either row address or chip id that doubles capacity if it's ever used.