4 ms·
The chips using preliminary/draft specs are annoying. However RISC-V has allocations dedicated in the ISA for vendor specific instructions which is fine. Code t
by anfilt 4y ago
The chips using preliminary/draft specs are annoying. However RISC-V has allocations dedicated in the ISA for vendor specific instructions which is fine. Code that does not use such extensions runs just fine
- snvzz 4y ago>The chips using preliminary/draft specs are annoying. They actually aren't annoying at all. Real world testing with actual chips is very helpful to the RISC-V Foundation and its extension development and ratification process.