>"In a RISC architecture, every memory access is a register load or store, and our task would be completely impossible. But x86 does not have this property." I

>"In a RISC architecture, every memory access is a register load or store, and our task would be completely impossible. But x86 does not have this property." In any architecture, including x86, every memory access is an ALU load or store, and our task would be completely impossible. >"But x86 does not have this property." The x86 does have this property(!) -- but it is hidden/abstracted away from the programmer -- by the use of x86 microcode between x86 instructions -- and the ALU... But -- an interesting and educational article nonetheless... All x86 registers -- are basically just abstracted views of an ALU and/or Memory (both possibilities are merged into one "view", depending on which CPU operation happened last!) -- which is now may be cached by the CPU (as opposed to being a direct view of the ALU) -- at a given CPU/ALU state/time...(!) https://www.joelonsoftware.com/2002/11/11/the-law-of-leaky-abstractions/ https://www.joelonsoftware.com/2002/11/11/the-law-of-leaky-a...