4 ms·

… which is another testament to the fact that a wide memory bus is an attribute of server or hi-end components rather than «laptop parts» that one can throw int

… which is another testament to the fact that a wide memory bus is an attribute of server or hi-end components rather than «laptop parts» that one can throw into a bucket, stir vigorously, cook on a slow fire and get a M1 Ultra with a 1024-bit wide memory bus. I ought to have used «typically» rather than «currently» as wide memory buses were coming and going more mainstream in the server space, whilst not yet being widely available today. The hardware transition cycle will take a few years, and as of today «currently» still holds true, semantically and factually, as cloud platforms and data centres run nearly entirely exclusively on Xeon something Lake and EPYC 3rd Gen CPU's, and neither has such a wide memory bus. > … per socket. Does that mean that 2x socketable EPYC CPU's (say, 512-bit wide each) will be able to access RAM via a 1x 1024-bit wide memory bus? If yes, how will access to RAM work, i.e. access multiplexing – memory banks? time interleaved access? something else?

wtallis 4y ago
> Does that mean that 2x socketable EPYC CPU's (say, 512-bit wide each) will be able to access RAM via a 1x 1024-bit wide memory bus? No. All recent dual-socket platforms are NUMA, meaning a CPU only has fast access to its local memory, and accessing memory attached to the other CPU socket requires going through a slower link between sockets. NUMA-aware operating systems and applications try to avoid allocating memory on a different NUMA node than the processor cores that will be using that memory. On AMD EPYC, the internal structure of the IO die (memory controller) means it is sometimes advantageous to enable the option for the system to report more than one NUMA node per socket.
- inkyoto 4y ago
  I am no stranger to NUMA since SGI days, and AMD EPYC is a ccNUMA. If I read it correctly, 512- and 768-bit wide memory bus is available to access the socketed CPU's local memory only (which is relatively small), and access to the shared memory (which is large to very large) seems to be still via a switched Infinity Fabric memory controller. How wide is the Infinity Fabric nowadays? I can't easily find the conclusive evidence.

wtallis 4y ago

> Does that mean that 2x socketable EPYC CPU's (say, 512-bit wide each) will be able to access RAM via a 1x 1024-bit wide memory bus? No. All recent dual-socket platforms are NUMA, meaning a CPU only has fast access to its local memory, and accessing memory attached to the other CPU socket requires going through a slower link between sockets. NUMA-aware operating systems and applications try to avoid allocating memory on a different NUMA node than the processor cores that will be using that memory. On AMD EPYC, the internal structure of the IO die (memory controller) means it is sometimes advantageous to enable the option for the system to report more than one NUMA node per socket.

inkyoto 4y ago
I am no stranger to NUMA since SGI days, and AMD EPYC is a ccNUMA. If I read it correctly, 512- and 768-bit wide memory bus is available to access the socketed CPU's local memory only (which is relatively small), and access to the shared memory (which is large to very large) seems to be still via a switched Infinity Fabric memory controller. How wide is the Infinity Fabric nowadays? I can't easily find the conclusive evidence.