I can see mapping CS to 1MB and DS, ES, and SS all to another 1MB for 2MB as moderately viable. This would make the system a Harvard Architecture instead of a

I can see mapping CS to 1MB and DS, ES, and SS all to another 1MB for 2MB as moderately viable. This would make the system a Harvard Architecture instead of a von Neumann, with the escape hatch of segment prefixes. It would be even more of a nightmare to program than the already janky segmented memory model we ended up with, so I'm happy IBM wisely decided to avoid it.