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> […] and the insides are now laptop parts. The Mac Studio is simply the desktop computer that gets the Macbook Pro chips. «Laptop parts» connect M1 CPU cluste

> […] and the insides are now laptop parts. The Mac Studio is simply the desktop computer that gets the Macbook Pro chips. «Laptop parts» connect M1 CPU clusters to RAM via a 512-bit wide (M1 Max) and a 1024-bit wide (M1 Ultra) memory bus yielding 100 Gb/sec (per a CPU core), 200 Gb/sec (per a CPU cluster) and 400 (M1 Max)/800 (M1 Ultra) Gb/sec cumulative data transfer speeds. GPU and ANE cores access the main memory via the same wide memory bus. L1 caches (I+D) are 128kB+64 kb (efficiency cores) and 192+128 kb (performance); L2 caches are 24 Mb (M1 Max) and 48 Mb (M1 Ultra), and L3 cache is 48 Mb (Max) and 96 Mb (Ultra). Auxiliary tasks (disk encryption, video encoding/decoding etc) are off-loaded to dedicated processing units which is reminiscent to that a typical mainframe architecture with channel processors and channel programmes rather than that of a laptop. Most «hi-end» servers today do not come anywhere close to such configurations leave alone the form factor and the net system efficiency. 512-bit wide memory bus is currently only found inside hi-end GPU cards, and the compute off-loading / accelerating units are an add-on feature for a server that may or may not be available. Only POWER10 and Telum systems from IBM offer similar (albeit far more scalable and feature rich) designs and at a completely different price scale.

wtallis 4y ago
> 512-bit wide memory bus is currently only found inside hi-end GPU cards, AMD EPYC CPUs just went from 512-bit DDR4 to 768-bit DDR5, per socket.
- inkyoto 4y ago
  … which is another testament to the fact that a wide memory bus is an attribute of server or hi-end components rather than «laptop parts» that one can throw into a bucket, stir vigorously, cook on a slow fire and get a M1 Ultra with a 1024-bit wide memory bus. I ought to have used «typically» rather than «currently» as wide memory buses were coming and going more mainstream in the server space, whilst not yet being widely available today. The hardware transition cycle will take a few years, and as of today «currently» still holds true, semantically and factually, as cloud platforms and data centres run nearly entirely exclusively on Xeon something Lake and EPYC 3rd Gen CPU's, and neither has such a wide memory bus. > … per socket. Does that mean that 2x socketable EPYC CPU's (say, 512-bit wide each) will be able to access RAM via a 1x 1024-bit wide memory bus? If yes, how will access to RAM work, i.e. access multiplexing – memory banks? time interleaved access? something else?
  - wtallis 4y ago
    > Does that mean that 2x socketable EPYC CPU's (say, 512-bit wide each) will be able to access RAM via a 1x 1024-bit wide memory bus? No. All recent dual-socket platforms are NUMA, meaning a CPU only has fast access to its local memory, and accessing memory attached to the other CPU socket requires going through a slower link between sockets. NUMA-aware operating systems and applications try to avoid allocating memory on a different NUMA node than the processor cores that will be using that memory. On AMD EPYC, the internal structure of the IO die (memory controller) means it is sometimes advantageous to enable the option for the system to report more than one NUMA node per socket.
    - inkyoto 4y ago
      I am no stranger to NUMA since SGI days, and AMD EPYC is a ccNUMA. If I read it correctly, 512- and 768-bit wide memory bus is available to access the socketed CPU's local memory only (which is relatively small), and access to the shared memory (which is large to very large) seems to be still via a switched Infinity Fabric memory controller. How wide is the Infinity Fabric nowadays? I can't easily find the conclusive evidence.

wtallis 4y ago

> 512-bit wide memory bus is currently only found inside hi-end GPU cards, AMD EPYC CPUs just went from 512-bit DDR4 to 768-bit DDR5, per socket.

inkyoto 4y ago
… which is another testament to the fact that a wide memory bus is an attribute of server or hi-end components rather than «laptop parts» that one can throw into a bucket, stir vigorously, cook on a slow fire and get a M1 Ultra with a 1024-bit wide memory bus. I ought to have used «typically» rather than «currently» as wide memory buses were coming and going more mainstream in the server space, whilst not yet being widely available today. The hardware transition cycle will take a few years, and as of today «currently» still holds true, semantically and factually, as cloud platforms and data centres run nearly entirely exclusively on Xeon something Lake and EPYC 3rd Gen CPU's, and neither has such a wide memory bus. > … per socket. Does that mean that 2x socketable EPYC CPU's (say, 512-bit wide each) will be able to access RAM via a 1x 1024-bit wide memory bus? If yes, how will access to RAM work, i.e. access multiplexing – memory banks? time interleaved access? something else?
- wtallis 4y ago
  > Does that mean that 2x socketable EPYC CPU's (say, 512-bit wide each) will be able to access RAM via a 1x 1024-bit wide memory bus? No. All recent dual-socket platforms are NUMA, meaning a CPU only has fast access to its local memory, and accessing memory attached to the other CPU socket requires going through a slower link between sockets. NUMA-aware operating systems and applications try to avoid allocating memory on a different NUMA node than the processor cores that will be using that memory. On AMD EPYC, the internal structure of the IO die (memory controller) means it is sometimes advantageous to enable the option for the system to report more than one NUMA node per socket.
  - inkyoto 4y ago
    I am no stranger to NUMA since SGI days, and AMD EPYC is a ccNUMA. If I read it correctly, 512- and 768-bit wide memory bus is available to access the socketed CPU's local memory only (which is relatively small), and access to the shared memory (which is large to very large) seems to be still via a switched Infinity Fabric memory controller. How wide is the Infinity Fabric nowadays? I can't easily find the conclusive evidence.