3 ms·

This shocked me a little: > the 8088 has a 4-byte prefetch queue instead of a 6-byte prefetch queue My whole professional life, I've been led to believe that

by ajross 4y ago

This shocked me a little: > the 8088 has a 4-byte prefetch queue instead of a 6-byte prefetch queue My whole professional life, I've been led to believe that an 8088 is just an 8086 with a tiny state machine bolted in front of the bus to split multiword accesses. That it has design differences is really surprising. If the prefetch queue is smaller, then... what are they putting in that die area? Or did they redo the layout in other ways?

kens 4y ago
The 8088 die is almost the same as the 8086, but there are a few differences. There are two prefetch queue registers instead of three. But the 8088 queue registers are slightly more complicated because the chip needs to write one byte at a time instead of one word. So there's just a small gap in the layout. There are various changes in the memory cycle circuitry. And there are a few changes to the microcode. Once I finish with the 8086, I plan to look at the changes in the 8088 more closely.
adrian_b 4y ago
This difference between 8088 and 8086 was used by several MS-DOS programs to detect the type of the CPU on which they were run. It was easy to measure the length of the prefetch queue by a self-modifying program, which replaced the instruction placed 4 bytes after the current instruction pointer. On an 8088, the new instruction was executed, while on an 8086 the old instruction was executed. Various other such obscure differences (e.g. the value of a pushed stack pointer or the result of a shift operation with a shift count greater than the register size) were used to identify NEC V20 and V30, Intel 80186, 80188, 80286 and 80386, because architectural identification means, like the CPUID instruction, have been introduced only in Intel Pentium and in the late 486 models that were launched after Pentium.
- robocat 4y ago
  > It was easy to measure the length of the prefetch queue by a self-modifying program It became hard on the 386, as linked in the article: http://www.rcollins.org/secrets/PrefetchQueue.html http://www.rcollins.org/secrets/PrefetchQueue.html
- userbinator 4y ago
  The P6 family was when Intel decided to add circuitry to detect SMC and flush the queue, effectively making it appear to have a queue size of 0. AFAIK all x86 henceforth have been the same.
  - kens 4y ago
    I tried to track this down but I found sources claiming this was added to the 486, Pentium, and Pentium Pro (P6). So if you know for sure that it's P6, please let me know the details.
    - userbinator 4y ago
      https://news.ycombinator.com/item?id=33928876 https://news.ycombinator.com/item?id=33928876 Coincidentally a topic I did some reseach into recently. It appears to be in both the Pentium(P5/54) and PPro(P6), but not the 486.
- shadowofneptune 4y ago
  Official Intel program to detect the current processor (starts on page 16): http://kib.kiev.ua/x86docs/Intel/AppNote485/241618-005-mn.pdf http://kib.kiev.ua/x86docs/Intel/AppNote485/241618-005-mn.pd...
  - rep_lodsb 4y ago
    It may be official, but relying on undefined flags can fail: http://www.rcollins.org/ddj/Sep96/Sep96.html http://www.rcollins.org/ddj/Sep96/Sep96.html http://www.rcollins.org/ddj/Nov96/Nov96.html http://www.rcollins.org/ddj/Nov96/Nov96.html For detecting 8086(/88) and NEC V30(/20) vs. 80186 and anything later, I'd recommend using a shift instruction with a count of 33. The 186 and later processors will mask it with 0x1F, resulting in a shift by 1 instead. A shift count of 32 would also behave differently, but not set any flags because a shift by 0 effectively becomes a NOP. This is true even on x86-64, only for 64 bit operands is the count masked with 0x3F.
rep_lodsb 4y ago
Intel removed / disabled the last two bytes in the prefetch queue because they found that it actually made the CPU faster (because of less wasted prefetch cycles on jump instructions). The 8086 didn't have that problem, because it only started a new prefetch when there were two bytes free in the queue, so there was enough time for the jump microcode to stop it. edit: already mentioned in the article

by ajross 4y ago

kens 4y ago

The 8088 die is almost the same as the 8086, but there are a few differences. There are two prefetch queue registers instead of three. But the 8088 queue registers are slightly more complicated because the chip needs to write one byte at a time instead of one word. So there's just a small gap in the layout. There are various changes in the memory cycle circuitry. And there are a few changes to the microcode. Once I finish with the 8086, I plan to look at the changes in the 8088 more closely.

adrian_b 4y ago

This difference between 8088 and 8086 was used by several MS-DOS programs to detect the type of the CPU on which they were run. It was easy to measure the length of the prefetch queue by a self-modifying program, which replaced the instruction placed 4 bytes after the current instruction pointer. On an 8088, the new instruction was executed, while on an 8086 the old instruction was executed. Various other such obscure differences (e.g. the value of a pushed stack pointer or the result of a shift operation with a shift count greater than the register size) were used to identify NEC V20 and V30, Intel 80186, 80188, 80286 and 80386, because architectural identification means, like the CPUID instruction, have been introduced only in Intel Pentium and in the late 486 models that were launched after Pentium.

robocat 4y ago
> It was easy to measure the length of the prefetch queue by a self-modifying program It became hard on the 386, as linked in the article: http://www.rcollins.org/secrets/PrefetchQueue.html http://www.rcollins.org/secrets/PrefetchQueue.html
userbinator 4y ago
The P6 family was when Intel decided to add circuitry to detect SMC and flush the queue, effectively making it appear to have a queue size of 0. AFAIK all x86 henceforth have been the same.
- kens 4y ago
  I tried to track this down but I found sources claiming this was added to the 486, Pentium, and Pentium Pro (P6). So if you know for sure that it's P6, please let me know the details.
  - userbinator 4y ago
    https://news.ycombinator.com/item?id=33928876 https://news.ycombinator.com/item?id=33928876 Coincidentally a topic I did some reseach into recently. It appears to be in both the Pentium(P5/54) and PPro(P6), but not the 486.
shadowofneptune 4y ago
Official Intel program to detect the current processor (starts on page 16): http://kib.kiev.ua/x86docs/Intel/AppNote485/241618-005-mn.pdf http://kib.kiev.ua/x86docs/Intel/AppNote485/241618-005-mn.pd...
- rep_lodsb 4y ago
  It may be official, but relying on undefined flags can fail: http://www.rcollins.org/ddj/Sep96/Sep96.html http://www.rcollins.org/ddj/Sep96/Sep96.html http://www.rcollins.org/ddj/Nov96/Nov96.html http://www.rcollins.org/ddj/Nov96/Nov96.html For detecting 8086(/88) and NEC V30(/20) vs. 80186 and anything later, I'd recommend using a shift instruction with a count of 33. The 186 and later processors will mask it with 0x1F, resulting in a shift by 1 instead. A shift count of 32 would also behave differently, but not set any flags because a shift by 0 effectively becomes a NOP. This is true even on x86-64, only for 64 bit operands is the count masked with 0x3F.

rep_lodsb 4y ago

Intel removed / disabled the last two bytes in the prefetch queue because they found that it actually made the CPU faster (because of less wasted prefetch cycles on jump instructions). The 8086 didn't have that problem, because it only started a new prefetch when there were two bytes free in the queue, so there was enough time for the jump microcode to stop it. edit: already mentioned in the article