I love these. kens, nitpick on your first footnote: In fact the Apple II was designed for 4k DRAMs with a whole-cycle time of 500ns, which was the low end of

I love these. kens, nitpick on your first footnote: In fact the Apple II was designed for 4k DRAMs with a whole-cycle time of 500ns, which was the low end of the range in 1977. The idea is that the machine double pumps a 2MHz memory bus, with cycles alternating between the 1 MHz 6502 and the video scan circuitry (which doubles as the refresh controller). By the advent of 4164 chips, DRAM cycle rates were pushing 4MHz. But Woz was stuck with more limited hardware. Similarly the 8086 bus is multiplexed between address and data, a memory access is 4 cycles. So a 4.77 MHz IBM PC was actually cycling the DRAM at just 1.2MHz (though with no clever tricks, as MDA/CGA had physically separate framebuffers; there the extra bandwidth really was wasted). Which isn't to say that the footnote is wrong, just that "DRAM was faster than CPUs" is only part of the story.