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Stack-based CPUs didn't lose out to accumulator-based CPUs; the x87 for example was stack-based (and was originally intended to support the hardware stack trans
by cperciva 4y ago
Stack-based CPUs didn't lose out to accumulator-based CPUs; the x87 for example was stack-based (and was originally intended to support the hardware stack transparently overflowing to RAM -- but they didn't write the software to support that before the chip shipped).
But both of them lost out to many-general-purpose-registers based CPUs, because that's what you need in order to write code which has many instructions in flight at once (for superscalar, pipelined, or both). If you look at the FPU on the Pentium you see the nightmare you run into otherwise -- optimized Pentium x87 code is half FXCH (swap the top of stack with something else) instructions because the FPU was pipelined and so you had to keep shuffling your stack in order to avoid pipeline stalls. The Pentium FPU has a hefty register-renaming unit in order to make this work; if it had been designed with general purpose registers rather than as a stack, that would have been avoided.
- fanf2 4y agoIn 1993-4 I was an intern at Inmos, when they were trying to get the T9000 transputer to work. The transputer was a stack architecture, with a bytecode-style instruction set. The stack was shallow, just big enough to evaluate a typical expression you would write in a high-level language. It also had a local addressing mode, relative to a “workspace” pointer register, which was used for local variables. To make the T9 go faster, they gave it a “workspace cache”, which was effectively a register file. The instruction decoder would collect up sequences of bytecodes and turn them into RISC-style ops that worked directly on the registers, so the stack was in effect JITted away by the CPU’s front end. A really cool way to revamp an old design; a pity that the T9 was horribly buggy and never reached its performance goals :-(