It's not memory bandwidth entirely. Modern superscalar Out-of-Order CPUs rename architectural registers with some number of physical registers to make larger O

It's not memory bandwidth entirely. Modern superscalar Out-of-Order CPUs rename architectural registers with some number of physical registers to make larger OoO windows useful. To accomplish the same thing on a stack based architecture, you now have to rename memory addresses so that otherwise independent instructions can be reordered. The tags for registers are maybe 8-9 bits in a modern CPU, whereas full 64 bit tags would be needed for a stack based CPU (maybe you could get away with 48 bits on x86-64). That means more bits to compare in critical CPU blocks, which means more area and more power. You could relieve that pressure by doing register windows (like SPARC or ia64) that aren't in "memory", and those architectures did have performance benefits for certain workloads (I remember working on i960 where interrupts were shockingly fast for the number of registers it had), but those architectures never really took any significant share of the mainstream market. Architecture matters far less in modern CPUs so long as it doesn't do anything that makes it "too hard" to build a good superscalar OoO core. All that said, nobody has ever invested the kind of money put into x86 and ARM to make a stack based CPU go fast, so maybe the problems above are not insurmountable. But that's not the universe we happen to reside in.