3 ms·

Would love Mashey’s thoughts on RISC V, but AFAICT he left the business a couple of decades ago.

• zozbot234 4y ago
  Yes but RISC-V is very risc-y by the criteria Mashey proposes here. The one thing that arguably doesn't completely fit is the multiple insn sizes, and even then real-world RISC-V implementations have only two, at 2 or 4 bytes. That's still very low compared to historical CISC. And I think the atomic instructions do RMW to memory, but they carefully avoid complicated address modes; they even dispense with register+immediate offset. (The E variety of RISC-V is also a bit strange in having only 16 integer registers, but the rationale for that was supporting smaller chips and easier extensibility; it's still very clearly a load-store architecture where compute happens within registers. Arguably, compilers have also gotten better at staying within fewer registers and not spilling to memory. So "number of registers" as a criteria might have shifted a little bit.)
  • 33985868 4y ago
    MIPS did it too with the MIPS16 extension (https://en.wikipedia.org/wiki/MIPS_architecture#Application-specific_extensions https://en.wikipedia.org/wiki/MIPS_architecture#Application-...) Makes sense as a hardware designer to be able to pick a power- and space-efficient chip. Mashey also had thoughts about that: https://yarchive.net/comp/mips16.html https://yarchive.net/comp/mips16.html Likewise for atomic operations: https://yarchive.net/comp/ll_sc.html https://yarchive.net/comp/ll_sc.html
  • Tuna-Fish 4y ago
    > The one thing that arguably doesn't completely fit is the multiple insn sizes, and even then real-world RISC-V implementations have only two, at 2 or 4 bytes. They will have a third very soon. The encoding space for 4-byte instructions is almost spent.