5 ms·

Since then... was a decade ago (not 30 years) https://twitter.com/philae2014/status/427842417920712704 https://twitter.com/philae2014/status/427842417920712704

by shagie 4y ago

Since then... was a decade ago (not 30 years) https://twitter.com/philae2014/status/427842417920712704 https://twitter.com/philae2014/status/427842417920712704 https://www.cpushack.com/2014/11/12/here-comes-philae-powered-by-an-rtx2010/ https://www.cpushack.com/2014/11/12/here-comes-philae-powere... > Why was the RTX2010 chosen? Simply put the RTX2010 is the lowest power budget processor available that is radiation hardened, and powerful enough to handle the complex landing procedure. Philae runs on batteries for the first phase of its mission (later it will switch to solar/back up batteries) so the power budget is critical. The RTX2010 is a Forth based stack processor which allows for very efficient coding, again useful for a low power budget. > Eight of the instruments are also powered by a RTX2010s, making 10 total (running at between 8-10MHz). The lander also includes an Analog Devices ADSP-21020 and a pair of 80C3x microcontrollers as well as multiple FPGAs. However... more recently: Insight - https://www.jpl.nasa.gov/news/press_kits/insight/launch/mission/spacecraft/ https://www.jpl.nasa.gov/news/press_kits/insight/launch/miss... > The computer's core is a radiation-hardened central processor with PowerPC 750 architecture called RAD 750. This processor operates at 115.5 megahertz speed, compared with 20 megahertz speed of the RAD6000 processor used on Mars Phoenix. https://www.engadget.com/nasa-perseverance-powerpc-750-171516292.html https://www.engadget.com/nasa-perseverance-powerpc-750-17151... > When NASA's Perseverance guided itself to the surface of Mars on February 18th, it did so with the help of the same processor that powered the 1998 iMac G3. You know, the colorful and bulbous all-in-one desktop that saved Apple's business and helped it become the company it is today. According to the New Scientist (via Gizmodo), NASA's latest rover features an offshoot of the PowerPC 750 CPU. That processor is about 23 years old in 2021. The answer appears to be "more powerful processors have been designed that are radiation hardened. That said... while the hardware isn't as common today, a lot of virtual machines are based off of a stack based architecture - from the JVM to Webassembly to the Ethereum EVM.

opensores 4y ago
(some rambling questions here that are only semi-related:) NASA is really anal about radiation concerns, insisting the caches have ECC (or they run it with cache disabled). For the instruction cache this makes sense (as well as any higher caches that would store instructions). With modern CPU's having so many cores and threads being so cheap, couldn't NASA use these for redundancy? My second question, how much more resilient are older processes with larger feature size compared to modern 6/7nm ? Compare modern with older (14nm/22nm finfet, 28nm/32 soi) and ancient (65nm or larger).
- toast0 4y ago
  > With modern CPU's having so many cores and threads being so cheap, couldn't NASA use these for redundancy? Maybe? But CPU cost basically doesn't matter compared to launch cost. Power budget given the required computing needs during critical sections of the mission is probably the biggest priority after reliability. Modern cpus are good at compute/watt, but not necessarily at low watts at low load. No idea re: feature size, for cosmic rays and dram, it was thought that shrinking beyond some point was going to increase failures dramatically, but then it was fine. But in space radiation is more than cosmic rays.
- shagie 4y ago
  > With modern CPU's having so many cores and threads being so cheap, couldn't NASA use these for redundancy? Power constraints and heat dissipation constraints. https://arstechnica.com/science/2019/11/space-grade-cpus-how-do-you-send-more-computing-power-into-space/3/ https://arstechnica.com/science/2019/11/space-grade-cpus-how... > BAE RAD5545 is probably the most powerful radiation-hardened processor available today. Fabricated in the 45nm process, it is a 64-bit quad-core machine clocked at 466MHz with power dissipation of up to 20 Watts—and 20 Watts is a lot. A Quad Core i5 sitting in a 13-inch MacBook Pro 2018 is a 28 Watt processor. It can heat its thin aluminum chassis to really high temperatures up to a point where it becomes an issue for some users. Under more computationally intensive workloads, fans immediately kick in to cool the whole thing down. The only issue is that, in space, fans would do absolutely nothing, because there is no air they could blow onto a hot chip. The only possible way to get heat out of a spacecraft is through radiation, and that takes time. Sure, heat pipes are there to take excessive heat away from the processor, but this heat has to eventually go somewhere. Moreover, some missions have tight energy budgets, and they simply can’t use powerful processors like RAD5545 under such restrictions. That’s why the European GR740 has power dissipation at only 1.5 Watts. It’s not the fastest of the lot, but it is the most efficient. It simply gives you the most computational bang per Watt. The HPSC with 10 Watt power dissipation comes in at a close second, but not always.
  - nynx 4y ago
    45nm is massive for a high-performance processor. Rad-hardening compute is frankly overrated. Have multiple and compare state at a high-rate.
bjourne 4y ago
HotSpot VM is only using a stack for storing local variables when executing byte code. As soon as it needs to optimize a hot path it turns the byte code into register-based cpu-specific assembly.
- shagie 4y ago
  Very true... but its still a virtual stack machine. This gets into the "when you write the implementation or JIT" it is much easier to write something that doesn't use any registers and then target it to a machine that uses some number of registers than to write the VM for something that is register based, but then has different conventions for how to use those registers than the VM has... This is something that had to work on a 386, Sun Sparc, MIPS, Motorola 68030, Alpha, Vax (the CISCest instruction set you'll ever find https://documentation.help/VAX11/op_POLY.htm https://documentation.help/VAX11/op_POLY.htm )... and even its own Java Processor ( https://en.wikipedia.org/wiki/Java_processor https://en.wikipedia.org/wiki/Java_processor - https://www.usenix.org/legacy/publications/library/proceedings/jvm01/full_papers/aoki/aoki_html/index.html https://www.usenix.org/legacy/publications/library/proceedin... ). The difficulty would be if you made a... 32 register system and then you had to do the JIT from that to MIPS, but the frame pointer was foreign to the VM and $s0-$s7 where not ones you could touch without extra work... and then x86 had different conventions based on who wrote the compiler ( https://en.wikipedia.org/wiki/X86_calling_conventions#List_of_x86_calling_conventions https://en.wikipedia.org/wiki/X86_calling_conventions#List_o... )... It becomes much easier to work with a system with no registers and then make it "easier" to do the JIT than to do registers and then go from "too many" to trying to redo them for that system. And while it's not something I follow at all, apparently the EVM is also stack based. https://medium.com/mycrypto/the-ethereum-virtual-machine-how-does-it-work-9abac2b7c9e https://medium.com/mycrypto/the-ethereum-virtual-machine-how... > The EVM uses a 256-bit register stack from which the most recent 16 items can be accessed or manipulated at once. In total, the stack can only hold 1024 items. Which is... kind of interesting. Reminds me somewhat of dc - https://en.wikipedia.org/wiki/Dc_(computer_program) https://en.wikipedia.org/wiki/Dc_(computer_program) where its stack based, but has "registers" too (though you tend to use registers for storing macros which can then be loaded onto the stack and executed).

by shagie 4y ago

opensores 4y ago

(some rambling questions here that are only semi-related:) NASA is really anal about radiation concerns, insisting the caches have ECC (or they run it with cache disabled). For the instruction cache this makes sense (as well as any higher caches that would store instructions). With modern CPU's having so many cores and threads being so cheap, couldn't NASA use these for redundancy? My second question, how much more resilient are older processes with larger feature size compared to modern 6/7nm ? Compare modern with older (14nm/22nm finfet, 28nm/32 soi) and ancient (65nm or larger).

toast0 4y ago
> With modern CPU's having so many cores and threads being so cheap, couldn't NASA use these for redundancy? Maybe? But CPU cost basically doesn't matter compared to launch cost. Power budget given the required computing needs during critical sections of the mission is probably the biggest priority after reliability. Modern cpus are good at compute/watt, but not necessarily at low watts at low load. No idea re: feature size, for cosmic rays and dram, it was thought that shrinking beyond some point was going to increase failures dramatically, but then it was fine. But in space radiation is more than cosmic rays.
shagie 4y ago
> With modern CPU's having so many cores and threads being so cheap, couldn't NASA use these for redundancy? Power constraints and heat dissipation constraints. https://arstechnica.com/science/2019/11/space-grade-cpus-how-do-you-send-more-computing-power-into-space/3/ https://arstechnica.com/science/2019/11/space-grade-cpus-how... > BAE RAD5545 is probably the most powerful radiation-hardened processor available today. Fabricated in the 45nm process, it is a 64-bit quad-core machine clocked at 466MHz with power dissipation of up to 20 Watts—and 20 Watts is a lot. A Quad Core i5 sitting in a 13-inch MacBook Pro 2018 is a 28 Watt processor. It can heat its thin aluminum chassis to really high temperatures up to a point where it becomes an issue for some users. Under more computationally intensive workloads, fans immediately kick in to cool the whole thing down. The only issue is that, in space, fans would do absolutely nothing, because there is no air they could blow onto a hot chip. The only possible way to get heat out of a spacecraft is through radiation, and that takes time. Sure, heat pipes are there to take excessive heat away from the processor, but this heat has to eventually go somewhere. Moreover, some missions have tight energy budgets, and they simply can’t use powerful processors like RAD5545 under such restrictions. That’s why the European GR740 has power dissipation at only 1.5 Watts. It’s not the fastest of the lot, but it is the most efficient. It simply gives you the most computational bang per Watt. The HPSC with 10 Watt power dissipation comes in at a close second, but not always.
- nynx 4y ago
  45nm is massive for a high-performance processor. Rad-hardening compute is frankly overrated. Have multiple and compare state at a high-rate.

bjourne 4y ago

HotSpot VM is only using a stack for storing local variables when executing byte code. As soon as it needs to optimize a hot path it turns the byte code into register-based cpu-specific assembly.

shagie 4y ago
Very true... but its still a virtual stack machine. This gets into the "when you write the implementation or JIT" it is much easier to write something that doesn't use any registers and then target it to a machine that uses some number of registers than to write the VM for something that is register based, but then has different conventions for how to use those registers than the VM has... This is something that had to work on a 386, Sun Sparc, MIPS, Motorola 68030, Alpha, Vax (the CISCest instruction set you'll ever find https://documentation.help/VAX11/op_POLY.htm https://documentation.help/VAX11/op_POLY.htm )... and even its own Java Processor ( https://en.wikipedia.org/wiki/Java_processor https://en.wikipedia.org/wiki/Java_processor - https://www.usenix.org/legacy/publications/library/proceedings/jvm01/full_papers/aoki/aoki_html/index.html https://www.usenix.org/legacy/publications/library/proceedin... ). The difficulty would be if you made a... 32 register system and then you had to do the JIT from that to MIPS, but the frame pointer was foreign to the VM and $s0-$s7 where not ones you could touch without extra work... and then x86 had different conventions based on who wrote the compiler ( https://en.wikipedia.org/wiki/X86_calling_conventions#List_of_x86_calling_conventions https://en.wikipedia.org/wiki/X86_calling_conventions#List_o... )... It becomes much easier to work with a system with no registers and then make it "easier" to do the JIT than to do registers and then go from "too many" to trying to redo them for that system. And while it's not something I follow at all, apparently the EVM is also stack based. https://medium.com/mycrypto/the-ethereum-virtual-machine-how-does-it-work-9abac2b7c9e https://medium.com/mycrypto/the-ethereum-virtual-machine-how... > The EVM uses a 256-bit register stack from which the most recent 16 items can be accessed or manipulated at once. In total, the stack can only hold 1024 items. Which is... kind of interesting. Reminds me somewhat of dc - https://en.wikipedia.org/wiki/Dc_(computer_program) https://en.wikipedia.org/wiki/Dc_(computer_program) where its stack based, but has "registers" too (though you tend to use registers for storing macros which can then be loaded onto the stack and executed).