Is it likely they'll just offload the entire L3 onto a larger node sized chiplet to save both space and money? If 5nm and 3nm are the same SRAM size, no sense p

Is it likely they'll just offload the entire L3 onto a larger node sized chiplet to save both space and money? If 5nm and 3nm are the same SRAM size, no sense putting any L3 on the 3nm if the latency impact isn't too major.