4 ms·

For the first version of TSMC 3nm, die sizes are projected to be ~42% smaller than TSMC 5nm and you have a choice of using ~30% less power or improving performa

For the first version of TSMC 3nm, die sizes are projected to be ~42% smaller than TSMC 5nm and you have a choice of using ~30% less power or improving performance by ~15%. https://www.anandtech.com/show/17452/tsmc-readies-five-3nm-process-technologies-with-finflex https://www.anandtech.com/show/17452/tsmc-readies-five-3nm-p...

nsteel 4y ago
Unless your chip is mostly SRAM and lower power consumption isn't worth the massive cost of 3nm. It's not the normal easy decision for some designs.
- Latty 4y ago
  Hence AMD using different process nodes for the stuff that scales and the stuff that doesn't at the same time with their chiplets, so they can get the best of both worlds.
  - cma 4y ago
    Do they use different nodes for stacked 3d cache, since cache is scaling worse?
    - formerly_proven 4y ago
      3D V-Cache in the only SKUs on the market right now (5800X3D and Milan-X) is 7nm, just like the CCD beneath it. IOD is Glofo 12nm on that. On GPUs this strategy isn't working out too well for them right now. Their 7900 is a lot more silicon with a lot more transistors (300 mm² of N5, 220 mm² of N6, 58bn xtors) compared to the competition (380 mm² of N4, 46bn) [1] and is marginally faster in some cases, drastically slower in others, and uses much more power in every case. [1] While AMD uses two slightly older processes, AIUI the overall packaging and silicon costs are speculated to be quite a bit higher for AMD compared to nVidia here.
      - Latty 4y ago
        I don't think comparing chiplet sizes by summing the area is a good way of doing it, because smaller nodes cost more and have lower yield, and smaller individual chiplets mean way less loss per-wafer, as the bigger the size of a single usable unit, the more chance something is broken and it isn't usable. Losing one or two small chiplets is a lot cheaper than losing entire chips in a monolithic setup. AMD claim that producing a 16-core Ryzen CPU without chiplets would have cost them twice as much. You say that the GPU strategy isn't working out, but I think that really depends on what their pricing strategy is. I suspect they just don't feel they can take the market right now, and are making a lot of margin while the market will support it, rather than trying to compete on price at this moment, but I admittedly don't have any evidence for that. I guess we'll see, but it sure seems like there is a lot of advantage to building the way they have to me, I'd personally be surprised if it didn't pay off.
  - nsteel 4y ago
    Didn't AMD start down the chiplet path way before the horrible SRAM scaling became clear? I was the under the impression they were chasing better yield and this is just another handy gain.
ajross 4y ago
Worth pointing out that (5/3)^2 is MUCH higher than the 1.42 you cite though. It's definitely true that process scaling is employing tricks to increase density faster than feature size would predict. But it's even more true that node sizes from TSMC are now just totally made up nonsense. This is not remotely a full node kind of improvement.
- vardump 4y ago
  I think almost no one cares. While it's unlikely scaling continues to this level, I got this funny idea: eventually the marketing gate size might become smaller than a single atom!
  - monocasa 4y ago
    We're close enough to see that on the horizon; about 2 angstroms is the width of a silicon atom. Or well, distance between two nuclei in a silicon lattice. 'Width' of an atom is a tricky concept with many definitions.
    - ghayes 4y ago
      For those out of date on units, 2 angstrom is 0.2nm.
- kurthr 4y ago
  Well, to be fair it's a full node price increase! It's the first node where each transistor is more expensive. :^)

nsteel 4y ago

Unless your chip is mostly SRAM and lower power consumption isn't worth the massive cost of 3nm. It's not the normal easy decision for some designs.

Latty 4y ago
Hence AMD using different process nodes for the stuff that scales and the stuff that doesn't at the same time with their chiplets, so they can get the best of both worlds.
- cma 4y ago
  Do they use different nodes for stacked 3d cache, since cache is scaling worse?
  - formerly_proven 4y ago
    3D V-Cache in the only SKUs on the market right now (5800X3D and Milan-X) is 7nm, just like the CCD beneath it. IOD is Glofo 12nm on that. On GPUs this strategy isn't working out too well for them right now. Their 7900 is a lot more silicon with a lot more transistors (300 mm² of N5, 220 mm² of N6, 58bn xtors) compared to the competition (380 mm² of N4, 46bn) [1] and is marginally faster in some cases, drastically slower in others, and uses much more power in every case. [1] While AMD uses two slightly older processes, AIUI the overall packaging and silicon costs are speculated to be quite a bit higher for AMD compared to nVidia here.
    - Latty 4y ago
      I don't think comparing chiplet sizes by summing the area is a good way of doing it, because smaller nodes cost more and have lower yield, and smaller individual chiplets mean way less loss per-wafer, as the bigger the size of a single usable unit, the more chance something is broken and it isn't usable. Losing one or two small chiplets is a lot cheaper than losing entire chips in a monolithic setup. AMD claim that producing a 16-core Ryzen CPU without chiplets would have cost them twice as much. You say that the GPU strategy isn't working out, but I think that really depends on what their pricing strategy is. I suspect they just don't feel they can take the market right now, and are making a lot of margin while the market will support it, rather than trying to compete on price at this moment, but I admittedly don't have any evidence for that. I guess we'll see, but it sure seems like there is a lot of advantage to building the way they have to me, I'd personally be surprised if it didn't pay off.
- nsteel 4y ago
  Didn't AMD start down the chiplet path way before the horrible SRAM scaling became clear? I was the under the impression they were chasing better yield and this is just another handy gain.

ajross 4y ago

Worth pointing out that (5/3)^2 is MUCH higher than the 1.42 you cite though. It's definitely true that process scaling is employing tricks to increase density faster than feature size would predict. But it's even more true that node sizes from TSMC are now just totally made up nonsense. This is not remotely a full node kind of improvement.

vardump 4y ago
I think almost no one cares. While it's unlikely scaling continues to this level, I got this funny idea: eventually the marketing gate size might become smaller than a single atom!
- monocasa 4y ago
  We're close enough to see that on the horizon; about 2 angstroms is the width of a silicon atom. Or well, distance between two nuclei in a silicon lattice. 'Width' of an atom is a tricky concept with many definitions.
  - ghayes 4y ago
    For those out of date on units, 2 angstrom is 0.2nm.
kurthr 4y ago
Well, to be fair it's a full node price increase! It's the first node where each transistor is more expensive. :^)