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> TSMC's 3nm process showed practically no improvement in density over the company's previous 5nm node with respect to SRAM density SRAM is becoming a larger a
by sroussey 4y ago
> TSMC's 3nm process showed practically no improvement in density over the company's previous 5nm node with respect to SRAM density
SRAM is becoming a larger and larger percentage of area of many chips from both a need for more cache and from the fact that everything else is shrinking.
- sroussey 4y agoThis also makes for very expensive SRAM (paying for cutting edge 3nm pricing but only getting 5nm product). AMD is ahead of the curve here with their 3D cache, but that only helps L3+.
- Salgat 4y agoIs it likely they'll just offload the entire L3 onto a larger node sized chiplet to save both space and money? If 5nm and 3nm are the same SRAM size, no sense putting any L3 on the 3nm if the latency impact isn't too major.