10 ms·
> And because it's not clear how OS schedulers could nicely switch on-the-fly between cores with different instruction set capabilities, it's essentially not us
by _kbh_ 4y ago
> And because it's not clear how OS schedulers could nicely switch on-the-fly between cores with different instruction set capabilities, it's essentially not use-able.
Couldn't you implement the new instructions (even slowly) in microcode? so they support the instructions with minimal silicon, even if its as slow or slower then other vector instructions?.