The designs are all essentially the same, two levels of high speed SRAMs to give you segment/page tables. Some designs supported bigger SRAMS for more contexts.

The designs are all essentially the same, two levels of high speed SRAMs to give you segment/page tables. Some designs supported bigger SRAMS for more contexts. The schematics are all up on bitsavers. Originally, I had thought they came up with it at Stanford, but from memory it seems to be roughly the same setup used in the MIT CADR.