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I looked at simple examples (counters, fibonacci generator) of hardcaml in the github repo, but I don't see any obvious advantages over systemverilog, verilog,
by supahfly_remix 4y ago
I looked at simple examples (counters, fibonacci generator) of hardcaml in the github repo, but I don't see any obvious advantages over systemverilog, verilog, or VHDL (the industry standard languages). Why would one use hardcaml over these?
- jadbox 4y agoBut does VHDL work for FPGA?
- supahfly_remix 4y agoYes
- mijoharas 4y agoFrom the article: > We believe by using Hardcaml we were able to more efficiently and robustly come up with designs in the short competition period So, the authors seem to believe they are more productive in it than other languages, and seem to be positioning it as a competitive advantage.
- supahfly_remix 4y agoWhat abstractions does Hardcaml provide that makes them believe they are more productive in it?