4 ms·

As a high level language programmer, I look forward to understanding my computer all the way down i.e. including the ISA which is not happening on amd64.

FullyFunctional 4y ago
TSMC is not going to give up their trade secrets, sorry. Also, if you are using a high-end RISC-V (none on the market currently), then the implementation is going to be proprietary and decidedly non-trivial. I'm not sure in which sense you expect to "understand your computer".
- user3939382 4y ago
  This is a surprisingly snarky/nasty comment "sorry" > I'm not sure in which sense you expect to "understand How about this? https://riscv.org/technical/specifications/ https://riscv.org/technical/specifications/ If there are a few extensions buried in the chip that doesn't materially change what I said.
  - mike_hock 4y ago
    The equivalent manuals are available from Intel and AMD.
    - user3939382 4y ago
      The issue isn’t the manuals existing it’s what they describe. Basically the R in RISC.
- mike_hock 4y ago
  And you can definitely understand amd64 on an ISA level, which is the publicly documented "high" level interface.
  - user3939382 4y ago
    I didn’t find it accessible.
- sanxiyn 4y ago
  Well, you could go buy and read Fundamentals of Semiconductor Fabrication (I did). This should give you understanding comparable to reading The C Programming Language. Yes, it is shallower understanding than what you would get by writing a C compiler yourself or working at TSMC, but it definitely is still understanding.
connicpu 4y ago
For understanding what's going on all the way down to the ISA level, I'd say something like a PIC microcontroller is even easier since they tend to have only around 50 instructions, though RISC-V has the advantage that it could scale all the way up to potentially desktop CPUs some day
KMag 4y ago
MIT 6.004 was one of my favorite classes. I think you can probably find it on OpenCourseWare. Over the course of a semester, you work your way up from very basic transistor physics to basic logic gates to a DEC Alpha AXP-inspired CPU (but 32-bit instead of 64-bit, the program counter is one of the numbered registers, and the high bit of the program counter determines if it's in kernel or userspace mode) that you've designed at the logic gate level. There are test suites that run in a simulator (jsim), where the kernel includes emulation for multiply and divide instructions in the illegal operation trap handler... so as long as you've correctly implemented the most basic instructions, you can run some fairly complicated software in emulation. In the class, there were competitions for the highest benchmark scores (in emulation) and highest ratio of benchmark score to gate count (again, in emulation). The high performance implementations end up having 5 stage pipelines with bypass networks to avoid having to wait for intermediate results to hit the register file. I remember even having the carry logic in my ALU alternate the sense of the carry at every level up the tree in order to save one gate delay at each level. My year, I don't think anyone implemented register renaming, but I wouldn't put it past some students. I would love to see 6.004 switch from Beta to RISC-V and also for the Stanford compilers class to switch from MIPS to RISC-V.
- user3939382 4y ago
  Some of my education in this is from a book called Inside the Machine which I really enjoyed. I noticed I was able to easily understand the earlier architectures but at some point they got really complex and I didn’t find it accessible. I took a look at amd64 and it was like.. haha no. I’m sure I could learn it if I was spending every day with that layer but I’m not. From what I’ve seen of RISC I’m hopeful I can retain it even going long intervals without looking at it.

FullyFunctional 4y ago

TSMC is not going to give up their trade secrets, sorry. Also, if you are using a high-end RISC-V (none on the market currently), then the implementation is going to be proprietary and decidedly non-trivial. I'm not sure in which sense you expect to "understand your computer".

user3939382 4y ago
This is a surprisingly snarky/nasty comment "sorry" > I'm not sure in which sense you expect to "understand How about this? https://riscv.org/technical/specifications/ https://riscv.org/technical/specifications/ If there are a few extensions buried in the chip that doesn't materially change what I said.
- mike_hock 4y ago
  The equivalent manuals are available from Intel and AMD.
  - user3939382 4y ago
    The issue isn’t the manuals existing it’s what they describe. Basically the R in RISC.
mike_hock 4y ago
And you can definitely understand amd64 on an ISA level, which is the publicly documented "high" level interface.
- user3939382 4y ago
  I didn’t find it accessible.
sanxiyn 4y ago
Well, you could go buy and read Fundamentals of Semiconductor Fabrication (I did). This should give you understanding comparable to reading The C Programming Language. Yes, it is shallower understanding than what you would get by writing a C compiler yourself or working at TSMC, but it definitely is still understanding.

connicpu 4y ago

For understanding what's going on all the way down to the ISA level, I'd say something like a PIC microcontroller is even easier since they tend to have only around 50 instructions, though RISC-V has the advantage that it could scale all the way up to potentially desktop CPUs some day

KMag 4y ago

MIT 6.004 was one of my favorite classes. I think you can probably find it on OpenCourseWare. Over the course of a semester, you work your way up from very basic transistor physics to basic logic gates to a DEC Alpha AXP-inspired CPU (but 32-bit instead of 64-bit, the program counter is one of the numbered registers, and the high bit of the program counter determines if it's in kernel or userspace mode) that you've designed at the logic gate level. There are test suites that run in a simulator (jsim), where the kernel includes emulation for multiply and divide instructions in the illegal operation trap handler... so as long as you've correctly implemented the most basic instructions, you can run some fairly complicated software in emulation. In the class, there were competitions for the highest benchmark scores (in emulation) and highest ratio of benchmark score to gate count (again, in emulation). The high performance implementations end up having 5 stage pipelines with bypass networks to avoid having to wait for intermediate results to hit the register file. I remember even having the carry logic in my ALU alternate the sense of the carry at every level up the tree in order to save one gate delay at each level. My year, I don't think anyone implemented register renaming, but I wouldn't put it past some students. I would love to see 6.004 switch from Beta to RISC-V and also for the Stanford compilers class to switch from MIPS to RISC-V.

user3939382 4y ago
Some of my education in this is from a book called Inside the Machine which I really enjoyed. I noticed I was able to easily understand the earlier architectures but at some point they got really complex and I didn’t find it accessible. I took a look at amd64 and it was like.. haha no. I’m sure I could learn it if I was spending every day with that layer but I’m not. From what I’ve seen of RISC I’m hopeful I can retain it even going long intervals without looking at it.