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What do you think about the unusual choice for mask register semantics in RISC-V V which apparently forces chips to include silicon to support semantics nobody
by anonymoushn 4y ago
What do you think about the unusual choice for mask register semantics in RISC-V V which apparently forces chips to include silicon to support semantics nobody will actually want? https://www.computerenhance.com/p/the-problem-with-risc-v-v-mask-bits https://www.computerenhance.com/p/the-problem-with-risc-v-v-...
- zozbot234 4y agoIt's not "unusual"; using data registers for mask is a valid tradeoff especially for low-end implementations, whereas higher-end architectures can easily use shadow registers. Discussed in depth at https://github.com/riscv/riscv-v-spec/issues/811 https://github.com/riscv/riscv-v-spec/issues/811
- anonymoushn 4y agoIt's not "using data registers for mask" that is claimed to be unusual, it's requiring a the mask bit for the 64th byte of a comparison to be usable as as part of the 8th byte of a subsequent addition. I have read that, and it seems like the motivation is that someone who has written a PhD thesis thinks that people don't actually need filtering in their SIMD kernels, which is obviously ridiculous for general-purpose programs manually written in terms of vectors, but which may have been true for the particular programs under study.