IBM has been doing this for a long time. Eg here's one mainframe CPU with 960 MB of L4: https://fuse.wikichip.org/news/3383/ibm-doubles-its-14nm-edram-density-a

IBM has been doing this for a long time. Eg here's one mainframe CPU with 960 MB of L4: https://fuse.wikichip.org/news/3383/ibm-doubles-its-14nm-edram-density-adds-hundreds-of-megabytes-of-cache/ https://fuse.wikichip.org/news/3383/ibm-doubles-its-14nm-edr... (They also have DRAM in other levels of cache hierarchy except L1, with L2 running at 5+ GHz)