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There is a lot of benefit for scaling SRAM, because it makes up a large fraction of chip area on a lot of designs that use leading edge nodes (e.g., CPUs), and
by throwawaylinux 4y ago
There is a lot of benefit for scaling SRAM, because it makes up a large fraction of chip area on a lot of designs that use leading edge nodes (e.g., CPUs), and chip area ~= manufacturing cost for high volume products.
SRAM cells are constrained by certain features that are not able to shrink much
https://semiwiki.com/forum/index.php?threads/sram-cell-scaling.12722/ https://semiwiki.com/forum/index.php?threads/sram-cell-scali... the logical schematic of an SRAM does not show anything about how a real cell is physically constructed. Foundries and high end design companies have teams doing SRAM design.
- zozbot234 4y ago> Foundries and high end design companies have teams doing SRAM design. Yep, this is also why the claim in this article title might just be a bit overstated. There's a mention that TSMC will likely announce optimized SRAM cell designs for N3-like nodes at some point, and these designs can be expected to involve some scaling.
- nsteel 4y agoThe mention is that Wikichip expect optimized SRAM cells but there's nothing to support this. I'm not so sure given the problem they've had so far.