It's more likely that we will 3D stack our SRAM on top of (or underneath, depending on heat management) our logic chips, and there may be special SRAM-optimized

It's more likely that we will 3D stack our SRAM on top of (or underneath, depending on heat management) our logic chips, and there may be special SRAM-optimized processes if this occurs. 6T SRAM has a lot of issues in leading-edge process nodes that are optimized for logic, since it depends a lot on the analog characteristics of the transistors used. Separating SRAM and logic processes will eventually make sense if we find that SRAM and logic can't scale on the same process. L1 and L2 caches on the logic die can be 8T SRAM (which is, I think, already in the L1 cache of Intel CPUs) if needed.